yosys.git
2019-08-24 Eddie HungAlso add first.Q to chain_bits since variable length
2019-08-24 Eddie HungDo not enforce !EN_POLARITY on $dffe
2019-08-24 Eddie HungCreate new cell for fixed length SRL
2019-08-24 Eddie HungCleanup FDRE matching
2019-08-23 Eddie HungOops don't need a finally block
2019-08-23 Eddie HungKeep track of bits in variable length chain, to check...
2019-08-23 Eddie HungDon't forget $dff has no EN
2019-08-23 Eddie HungSame for variable length
2019-08-23 Eddie HungFilter on en_port for fixed length
2019-08-23 Eddie HungCheck clock is consistent
2019-08-23 Eddie HungFix last_cell.D
2019-08-23 Eddie HungRevert "Add a unique argument to pmgen's nusers()"
2019-08-23 Eddie HungRevert "Fix polarity"
2019-08-23 Eddie HungFix polarity
2019-08-23 Eddie HungCheck for non unique nusers/fanouts
2019-08-23 Eddie HungAdd a unique argument to pmgen's nusers()
2019-08-23 Eddie HungUpdate doc
2019-08-23 Eddie HungRemove (* init *) entry when consumed into SRL
2019-08-23 Eddie Hungindo -> into
2019-08-23 Eddie HungForgot to slice
2019-08-23 Eddie HungCope with possibility that D could connect to Q on...
2019-08-23 Eddie HungMention shregmap -tech xilinx is superseded
2019-08-23 Eddie Hungxilinx_srl now copes with word-level flops $dff{,e}
2019-08-23 Eddie Hungxilinx_srl to use 'slice' features of pmgen for word...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgen...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-23 Eddie HungForgot one
2019-08-23 Eddie HungPut abc_* attributes above port
2019-08-23 Eddie HungMerge pull request #1326 from mmicko/doc-update
2019-08-23 Clifford WolfFix port hanlding in pmgen
2019-08-23 Clifford WolfAdd pmgen slices and choices
2019-08-23 Miodrag MilanovicMake macOS depenency clear
2019-08-22 Eddie HungDo not propagate mem2reg attribute through to result
2019-08-22 Eddie HungIn sat: 'x' in init attr should not override constant
2019-08-22 Eddie HungRemove Xilinx test
2019-08-22 Eddie HungActually, there might not be any harm in updating sigmap...
2019-08-22 Eddie HungAdd comment as per @cliffordwolf
2019-08-22 Eddie HungAdd shregmap -tech xilinx test
2019-08-22 Eddie HungRevert "Try way that doesn't involve creating a new...
2019-08-22 Eddie HungTry way that doesn't involve creating a new wire
2019-08-22 Eddie HungIf d_bit already in sigbit_chain_next, create extra...
2019-08-22 Eddie HungSpelling
2019-08-22 Eddie HungMerge pull request #1322 from mmicko/pyosys_osx
2019-08-22 Eddie HungAdd doc
2019-08-22 Miodrag Milanovicdo not require boost if pyosys is not used
2019-08-22 Eddie HungMerge pull request #1319 from TeaEngineering/shuckc...
2019-08-22 Eddie HungAdd copyright
2019-08-22 Eddie HungAdd CHANGELOG entry
2019-08-22 Eddie HungRemove `shregmap -tech xilinx` additions
2019-08-22 Eddie Hungpmgen to also iterate over all module ports
2019-08-22 Eddie HungRemove output_bits
2019-08-22 Eddie HungForgot to set ud_variable.minlen
2019-08-22 Eddie HungDo not run xilinx_srl_pm in fixed loop
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
2019-08-22 Clifford WolfBump year in copyright notice
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1289 from mmicko/anlogic_fixes
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix
2019-08-22 Eddie HungCopy-paste typo
2019-08-22 Chris Shucksmithrequire tcl-tk in Brewfile
2019-08-22 Eddie HungRespect opt_expr -keepdc as per @cliffordwolf
2019-08-22 Eddie HungHandle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 Eddie HungAdd cover()
2019-08-22 Eddie HungCanonical form
2019-08-22 Clifford WolfMerge pull request #1316 from YosysHQ/eddie/fix_mem2reg
2019-08-22 Eddie HungAdd test
2019-08-22 Eddie Hungopt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-22 Eddie HungReuse var
2019-08-22 Eddie HungRevert "Trim shiftx_width when upper bits are 1'bx"
2019-08-22 Eddie Hungopt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-22 Eddie HungTrim shiftx_width when upper bits are 1'bx
2019-08-22 Eddie HungAdd comment
2019-08-22 Eddie HungAdd variable length support to xilinx_srl
2019-08-21 Eddie HungRename pattern to fixed
2019-08-21 Eddie Hungattribute -> attr
2019-08-21 Eddie HungUse Cell::has_keep_attribute()
2019-08-21 Eddie Hungabc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 Eddie Hungxilinx_srl to support FDRE and FDRE_1
2019-08-21 Eddie HungFix polarity of EN_POL
2019-08-21 whitequarkMerge pull request #1315 from mmicko/fix_dependencies
2019-08-21 Eddie HungAdd CLKPOL == 0
2019-08-21 Eddie HungReject if not minlen from inside pattern matcher
2019-08-21 Eddie HungGet wire via SigBit
2019-08-21 Eddie HungRespect \keep on cells or wires
2019-08-21 Eddie HungMerge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
2019-08-21 Eddie Hungmem2reg to preserve user attributes and src
2019-08-21 Eddie HungAdd init support
2019-08-21 Eddie HungFix spacing
2019-08-21 Eddie HungInitial progress on xilinx_srl
2019-08-21 Miodrag MilanovicFix test_pmgen deps
2019-08-21 Clifford WolfMerge pull request #1314 from YosysHQ/eddie/fix_techmap
2019-08-21 Eddie HungMissing newline
2019-08-21 Eddie HungFix copy-paste typo
2019-08-21 Eddie HungGrammar
2019-08-21 Eddie HungAdd test
2019-08-21 Eddie Hungtechmap -max_iter to apply to each module individually
2019-08-20 Eddie HungMerge pull request #1209 from YosysHQ/eddie/synth_xilinx
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