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yosys.git
2017-01-01
Clifford Wolf
Added cell port resizing to hierarchy pass
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2016-12-31
Clifford Wolf
Updated ABC to hg id 55cd83f432c0
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2016-12-31
Clifford Wolf
Bugfix in RTLIL::SigSpec::remove2()
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2016-12-29
Clifford Wolf
Updated ABC to hg id 8c6a635f7a20
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2016-12-29
Clifford Wolf
Improved write_json help message
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2016-12-26
Clifford Wolf
Updated ABC to hg id f591c081d5e7
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2016-12-24
Clifford Wolf
Merge pull request #284 from azonenberg/master
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2016-12-23
Andrew Zonenberg
Merge pull request #1 from azonenberg-hk/master
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2016-12-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-23
Clifford Wolf
Simplified log_spacer() code
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2016-12-22
Clifford Wolf
Added "yosys -W regex"
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2016-12-21
Clifford Wolf
Added AIGER back-end to automatic back-end detection
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2016-12-21
Clifford Wolf
Updated ABC to hg rev a4872e22c646
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2016-12-21
Clifford Wolf
Updated ABC to hg rev 8bab2eedbba4
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2016-12-21
Andrew Zonenberg
greenpak4: Added INT pin to GP_SPI
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2016-12-21
Andrew Zonenberg
greenpak4: removed unused MISO pin from GP_SPI
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2016-12-20
Andrew Zonenberg
greenpak4: Removed SPI_BUFFER parameter
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2016-12-20
Andrew Zonenberg
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
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2016-12-20
Andrew Zonenberg
greenpak4: Changed port names on GP_SPI for clarity
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2016-12-20
Andrew Zonenberg
greenpak4: Initial implementation of GP_SPI cell
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2016-12-17
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-17
Andrew Zonenberg
greenpak4: Updated GP_DCMP cell model
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2016-12-16
Andrew Zonenberg
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
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2016-12-15
Clifford Wolf
Added "verilog_defines" command
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2016-12-15
Andrew Zonenberg
greenpak4: Initial version of GP_DCMP skeleton (not...
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2016-12-14
Andrew Zonenberg
greenpak4: More fixups of GP_DCMPx cells
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2016-12-14
Andrew Zonenberg
greenpak4: And another typo :(
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2016-12-14
Andrew Zonenberg
greenpak4: Fixed another typo
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2016-12-14
Andrew Zonenberg
greenpak4: Fixed typo
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2016-12-14
Andrew Zonenberg
greenpak4: Cleaned up trailing spaces in cells_sim
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2016-12-14
Andrew Zonenberg
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
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2016-12-13
Clifford Wolf
Bugfix in comment handling
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2016-12-12
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-11
Clifford Wolf
Added $anyconst support to AIGER back-end
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2016-12-11
Clifford Wolf
Merge branch 'LSS-USP-unit-test-structure'
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2016-12-11
Clifford Wolf
Some minor CodingReadme changes in unit test section
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2016-12-11
Clifford Wolf
Build hotfix in tests/unit/Makefile
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2016-12-11
Andrew Zonenberg
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
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2016-12-10
rodrigosiqueira
Improved unit test structure
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2016-12-10
Andrew Zonenberg
greenpak4: Added support for inferred input/output...
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2016-12-10
Andrew Zonenberg
greenpak4: Can now techmap inferred D latches (without...
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2016-12-10
Andrew Zonenberg
greenpak4: Inverted D latch cells now have nQ instead...
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2016-12-06
Andrew Zonenberg
Added GP_DLATCH and GP_DLATCHI
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2016-12-06
Andrew Zonenberg
Initial implementation of techlib support for GreenPAK...
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2016-12-06
Andrew Zonenberg
Updated help text for synth_greenpak4
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2016-12-04
rodrigosiqueira
Added explanation about configure and create test
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2016-12-04
rodrigosiqueira
Added required structure to implement unit tests
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2016-12-03
Clifford Wolf
Added $assert/$assume support to AIGER back-end
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2016-12-03
Clifford Wolf
Improved yosys-smtbmc default -t/--assume-skipped for...
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2016-12-01
Clifford Wolf
Updated ABV to hg rev 8b555d9e67cf
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2016-12-01
Clifford Wolf
Added examples/aiger/
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2016-12-01
Clifford Wolf
Added "yosys-smtbmc --aig"
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2016-12-01
Clifford Wolf
Added support for partially initialized regs to smt2...
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2016-12-01
Clifford Wolf
Added "write_aiger -zinit -symbols -vmap"
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2016-11-30
Clifford Wolf
Added "write_aiger" command
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2016-11-30
Clifford Wolf
Added "design -reset-vlog"
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2016-11-29
Clifford Wolf
Improved equiv_purge log output
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2016-11-28
Clifford Wolf
Bugfix in smt2 back-end for pure checker modules
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2016-11-28
Clifford Wolf
Added support for macros as include file names
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2016-11-28
Clifford Wolf
Bugfix in "read_verilog -D NAME=VAL" handling
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2016-11-27
Clifford Wolf
Removed shebang line from smtio.py, fixes #279
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2016-11-23
Clifford Wolf
Added wire start_offset and upto handling BLIF back-end
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2016-11-23
Clifford Wolf
Added wire start_offset and upto handling to splitnets cmd
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2016-11-22
Clifford Wolf
Merge pull request #274 from oldtopman/lcurses
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2016-11-22
Clifford Wolf
Added "yosys-smtbmc --append"
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2016-11-22
oldtopman
Added optional flag for linking curses with readline.
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2016-11-19
Clifford Wolf
Merge pull request #272 from AlexDaniel/master
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2016-11-19
Aleks-Daniel...
Keep lines under 80 characters
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2016-11-19
Clifford Wolf
Improved ABC default scripts
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2016-11-19
Aleks-Daniel...
Markdownify README even further
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2016-11-19
Clifford Wolf
Merge pull request #271 from azidar/bugfix-assign-wmask
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2016-11-18
Adam Izraelevitz
Bugfix: include assign to write-mask
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2016-11-18
Clifford Wolf
More progress in FIRRTL back-end
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2016-11-17
Clifford Wolf
Progress in FIRRTL back-end
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2016-11-17
Clifford Wolf
Added first draft of FIRRTL back-end
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2016-11-16
Clifford Wolf
Cleanups and fixed in write_verilog regarding reg init
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2016-11-15
Clifford Wolf
Added support for hierarchical defparams
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2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
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2016-11-13
Clifford Wolf
Merge pull request #268 from AlexDaniel/master
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2016-11-12
Aleks-Daniel...
Markdownify README
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2016-11-09
Clifford Wolf
Minor bugfix in submod
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2016-11-08
Clifford Wolf
Progress in examples/gowin/
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2016-11-08
Clifford Wolf
Indenting fixes in gowin sim cell lib
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2016-11-08
Clifford Wolf
Bugfix in "setundef" pass
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2016-11-07
Clifford Wolf
Added examples/gowin/
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2016-11-05
Clifford Wolf
Implemented "scc -set_attr"
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2016-11-05
Clifford Wolf
Bugfix in "scc" command
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2016-11-04
Clifford Wolf
Fixed anonymous genblock object names
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2016-11-03
Clifford Wolf
Added hex constant support to write_verilog
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2016-11-03
Clifford Wolf
We are now in 0.7+ development
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2016-11-03
Clifford Wolf
Yosys 0.7
yosys-0.7
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2016-11-02
Clifford Wolf
Bugfix in "hierarchy -check"
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2016-11-02
Clifford Wolf
Updated command reference in manual
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2016-11-02
Clifford Wolf
Changelog for Yosys 0.7
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2016-11-02
Clifford Wolf
Added support for fsm_encoding="user"
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2016-11-02
Clifford Wolf
Added "fsm_expand -full"
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2016-11-01
Clifford Wolf
Some fixes in handling of signed arrays
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2016-11-01
Clifford Wolf
iCE40 flow is not experimental anymore
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2016-11-01
Clifford Wolf
Added initial version of "synth_gowin"
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2016-11-01
Clifford Wolf
Adde "write_verilog -renameprefix -v"
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