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yosys.git
2019-05-03
Clifford Wolf
Improve unused-detection for opt_clean driver-driver...
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2019-05-01
Clifford Wolf
Add additional test cases for for-loops
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2019-05-01
Clifford Wolf
Silently resolve completely unused cell-vs-const driver...
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2019-05-01
Clifford Wolf
Re-enable "final loop assignment" feature
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2019-04-30
Clifford Wolf
Fix segfault in wreduce
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2019-04-30
Clifford Wolf
Disabled "final loop assignment" feature
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2019-04-30
Clifford Wolf
Merge pull request #972 from YosysHQ/clifford/fix968
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2019-04-30
Clifford Wolf
Merge pull request #966 from YosysHQ/clifford/fix956
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2019-04-30
Clifford Wolf
Merge pull request #962 from YosysHQ/eddie/refactor_syn...
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2019-04-30
Clifford Wolf
Merge branch 'master' into eddie/refactor_synth_xilinx
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2019-04-30
Clifford Wolf
Merge pull request #973 from christian-krieg/feature...
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2019-04-30
Clifford Wolf
Include filename in "Executing Verilog-2005 frontend...
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2019-04-30
Clifford Wolf
Fix performance bug in RTLIL::SigSpec::operator==(...
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2019-04-30
Clifford Wolf
Add final loop variable assignment when unrolling for...
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2019-04-30
Clifford Wolf
Add handling of init attributes in "opt_expr -undriven"
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-30
Benedikt Tutzer
Cleaned up root directory
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2019-04-29
Clifford Wolf
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
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2019-04-29
Clifford Wolf
Merge pull request #967 from olegendo/depfile_esc_spaces
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2019-04-29
Oleg Endo
fix codestyle formatting
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2019-04-29
Oleg Endo
escape spaces with backslash when writing dep file
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2019-04-29
Clifford Wolf
Drive dangling wires with init attr with their init...
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2019-04-26
Eddie Hung
Where did this check come from!?!
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2019-04-26
Eddie Hung
Refactor synth_xilinx to auto-generate doc
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2019-04-26
Eddie Hung
Cleanup ice40
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2019-04-26
Eddie Hung
Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-25
Eddie Hung
Misspelling
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2019-04-23
Clifford Wolf
Merge pull request #957 from YosysHQ/oai4fix
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2019-04-23
David Shah
Fixes for OAI4 cell implementation
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2019-04-23
Eddie Hung
Format some names using inline code
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2019-04-23
Eddie Hung
Fix spelling
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2019-04-23
Clifford Wolf
Remove some left-over log_dump()
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2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
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2019-04-22
Eddie Hung
Update help message
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2019-04-22
Clifford Wolf
Merge pull request #952 from YosysHQ/clifford/fix370
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2019-04-22
Clifford Wolf
Merge pull request #951 from YosysHQ/clifford/logdebug
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2019-04-22
Clifford Wolf
Merge pull request #949 from YosysHQ/clifford/pmux2shim...
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2019-04-22
Clifford Wolf
Merge pull request #953 from YosysHQ/clifford/fix948
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2019-04-22
Eddie Hung
Move 'shregmap -tech xilinx' into map_cells
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2019-04-22
Clifford Wolf
Add support for zero-width signals to Verilog back...
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-22
Clifford Wolf
Determine correct signedness and expression width in...
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2019-04-22
Clifford Wolf
Add log_debug() framework
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2019-04-22
Clifford Wolf
Merge pull request #950 from whitequark/attrmap_remove_...
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2019-04-22
whitequark
attrmap: extend -remove to allow removing attributes...
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2019-04-22
Clifford Wolf
Updaye pmux2shiftx test
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2019-04-22
Clifford Wolf
Add full_pmux feature to pmux2shiftx
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2019-04-22
Clifford Wolf
Set ENABLE_LIBYOSYS=0 by default
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2019-04-22
Clifford Wolf
Set ENABLE_PYOSYS=0 by default
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'dh73-master'
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Re-added clean after techmap in synth_xilinx
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2019-04-22
Clifford Wolf
Merge pull request #916 from YosysHQ/map_cells_before_m...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-22
Clifford Wolf
Merge pull request #945 from YosysHQ/clifford/libwb
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2019-04-22
Clifford Wolf
Disable blackbox detection in techmap files
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2019-04-21
Eddie Hung
Tidy up, fix for -nosrl
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2019-04-21
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Eddie Hung
Add comments
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2019-04-21
Eddie Hung
Use new pmux2shiftx from #944, remove my old attempt
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2019-04-21
Luke Wren
ice40 cells_sim.v: SB_IO: update clock enable behaviour...
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2019-04-21
Clifford Wolf
Fix tests
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2019-04-21
Clifford Wolf
Add "noblackbox" attribute
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Clifford Wolf
New behavior for front-end handling of whiteboxes
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2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin' into xc7srl
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2019-04-20
Clifford Wolf
Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc
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2019-04-20
Clifford Wolf
Add "onehot" pass, improve "pmux2shiftx" onehot handling
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2019-04-20
Clifford Wolf
Add "techmap -wb", use in formal flows
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2019-04-20
Clifford Wolf
Check blackbox attribute in techmap/simplemap
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2019-04-20
Clifford Wolf
Add "wbflip" command
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2019-04-20
Clifford Wolf
Merge pull request #942 from YosysHQ/clifford/fix931
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2019-04-20
Clifford Wolf
Improve "pmux2shiftx"
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2019-04-19
Clifford Wolf
Fix some typos
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2019-04-19
Clifford Wolf
Improvements in "pmux2shiftx"
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2019-04-19
Clifford Wolf
Improvements in pmux2shiftx
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2019-04-19
Clifford Wolf
Add test for pmux2shiftx
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2019-04-19
Clifford Wolf
Improve pmux2shift ctrl permutation finder
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2019-04-19
Clifford Wolf
Complete rewrite of pmux2shiftx
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2019-04-19
Clifford Wolf
Import initial pmux2shiftx from eddieh
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2019-04-19
Clifford Wolf
Improve "show" handling of 0/1/X/Z padding
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2019-04-19
Clifford Wolf
Change "ne" to "neq" in btor2 output
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2019-04-19
Clifford Wolf
Add tests/aiger/.gitignore
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2019-04-19
Eddie Hung
Spelling fixes
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2019-04-19
Eddie Hung
Revert "write_json to not write contents (cells/wires...
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2019-04-18
Clifford Wolf
Update to ABC 3709744
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2019-04-18
Eddie Hung
Merge pull request #917 from YosysHQ/eddie/fix_retime
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2019-04-18
Eddie Hung
write_json to not write contents (cells/wires) of white...
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2019-04-18
Eddie Hung
Ignore 'whitebox' attr in flatten with "-wb" option
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2019-04-18
Eddie Hung
Fix abc's remap_name to not ignore [^0-9] when extracti...
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2019-04-18
Eddie Hung
ABC to call retime all the time
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2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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