gem5.git
2013-01-07 Andreas Sandbergtests: Create base classes to encapsulate common test...
2013-01-07 Ali Saidicache: add note about where conflicts are handled
2013-01-05 Nilay Vaishregressions: stats update due to decoder changes
2013-01-05 Gabe BlackDecoder: Remove the thread context get/set from the...
2013-01-05 Gabe BlackX86: Move address based decode caching in front of...
2013-01-05 Gabe BlackSPARC: Keep a copy of the current ASI in the decoder.
2013-01-05 Gabe BlackARM: Keep a copy of the fpscr len and stride fields...
2012-12-30 Nilay Vaishx86 regressions: stats update due to new x87 instructions
2012-12-30 Nilay Vaishx86: implement x87 fp instruction fnstsw
2012-12-30 Nilay Vaishx86: implement x87 fp instruction fsincos
2012-12-12 Nilay Vaisharm regressions: updates to config.ini, terminal files
2012-12-12 Nathanael Premillieuarm: set uopSet_uop as conditional or unconditional...
2012-12-12 Nathanael Premillieuarm: set movret_uop as conditional or unconditional...
2012-12-11 Nilay Vaishregressions: stats update due to stats from ruby prefetcher
2012-12-11 Nilay Vaishruby: add support for prefetching to MESI protocol
2012-12-11 Nilay Vaishruby: modify the directed tester to read/write streams
2012-12-11 Nilay Vaishruby: change slicc to allow for constructor args
2012-12-11 Nilay Vaishruby: add a prefetcher
2012-12-11 Nilay Vaishruby: add functions for computing next stride/page...
2012-12-06 Nilay Vaishregression test: update a couple of config.ini files
2012-12-06 Erik TomuskTournamentBP: Fix some bugs with table sizes and counters
2012-12-06 Malek Muslehinorder cpu: add missing DPRINTF argument
2012-12-06 Nathanael Premillieuo3 cpu: remove some unused buggy functions in the lsq
2012-11-19 Andreas Hanssonconfig: Fix description of checkpoint option from cycle...
2012-11-16 Nilay Vaishsim: have a curTick per eventq
2012-11-10 Nilay Vaishregressions: stats update due to ruby functional access...
2012-11-10 Nilay Vaishruby: support functional accesses in garnet flexible...
2012-11-10 Nilay Vaishruby: bug in functionalRead, revert recent changes
2012-11-08 Andreas Hanssonmem: Fix DRAM draining to ensure write queue is empty
2012-11-03 Lluis Vilanovax86, util: add m5_writefile to m5op_x86.S
2012-11-02 Hamid Reza... ruby: reset and dump stats along with reset of the...
2012-11-02 Ali Saidimem: fix use after free issue in memories until 4-phase...
2012-11-02 Ali Saidiupdate stats for preceeding changes
2012-11-02 Andreas Sandbergmem: Add support for writing back and flushing caches
2012-11-02 Andreas Sandbergsim: Add drain methods to request additional cleanup...
2012-11-02 Andreas Sandbergsim: Add SWIG interface for Serializable
2012-11-02 Andreas Sandbergpython: Rename doDrain()->drain() and make it do the...
2012-11-02 Andreas Sandbergsim: Reuse the code to change memory mode.
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergcpu: O3 add a header declaring the DerivO3CPU
2012-11-02 Andreas Sandbergcpu: Add header files for checker CPUs
2012-11-02 Andreas Sandbergdev: Fix ethernet device inheritance structure
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-11-02 Andreas Sandbergpci: Make Python wrapper cast to the right type
2012-11-02 Andreas Sandbergmips: Remove unused Python file
2012-11-02 Andreas Sandbergdev: Add missing inline declarations
2012-11-02 Andreas Sandbergbase: Add missing header file to addr_range.hh.
2012-10-09 James Clarksonm5: Expose m5 pseudo-instructions to C/C++ via a static...
2012-11-02 Dam SunwooARM: dump stats and process info on context switches
2012-11-02 Chander Sudanthibase: Fix a few incorrectly handled print format cases
2012-11-02 Chander Sudanthibase: split out the VncServer into a VncInput and Serve...
2012-11-02 Dam SunwooISA: generic Linux thread info support
2012-11-02 Ali Saidisim: Fix as issue where exit events on instr queues...
2012-11-02 Mrinmoy Ghosho3: Fix a couple of issues with the local predictor.
2012-11-02 Andreas SandbergPartly revert [4f54b0f229b5] and move draining to m5...
2012-10-31 Andreas Hanssonmem: Fix typo in port comments
2012-10-31 Andreas Hanssonstats: Update stats for fixed simple-atomic-mp config
2012-10-31 Andreas Hanssonconfig: Fix a typo in the simple-atomic-mp configuration
2012-10-30 Andreas Hanssonstats: Update stats for unified cache configuration
2012-10-30 Andreas Hanssonconfig: Unify caches used in regressions and adjust...
2012-10-27 Nilay Vaishregressions: update stats for ruby fs test
2012-10-27 Malek Muslehruby: set the is_icache param for caches
2012-10-27 Jason Power... Ruby: Use block size in configuring directory bits...
2012-10-26 Andreas Hanssonconfig: Add a check for fastmem only used with Atomic CPU
2012-10-26 Andreas Hanssonconfig: Remove unused mem_size in fs.py
2012-10-26 Andreas Hanssonconfig: Fix the cache class naming in regression scripts
2012-10-25 Andreas Hanssonstats: Update the stats to reflect the 1GHz default...
2012-10-25 Andreas Hanssondev: Make default clock more reasonable for system...
2012-10-25 Andreas Hanssonstats: Update stats to reflect use of SimpleDRAM
2012-10-25 Andreas Hanssonconfig: Use SimpleDRAM in full-system, and with o3...
2012-10-25 Andreas Hanssonconfig: Use shared cache config for regressions
2012-10-25 Andreas Hanssonarm: Use table walker clock that is inherited from CPU
2012-10-23 Andreas Hanssonstats: Update stats for DMA port send
2012-10-23 Andreas Hanssondev: Remove zero-time loop in DMA timing send
2012-10-23 Andreas Hanssonstats: Update t1000 stats to match recent changes
2012-10-18 Nilay Vaishruby: functional access updates to network test protocol
2012-10-16 Nilay Vaishregressions: update stats for eio tests
2012-10-16 Nilay Vaishregressions: update stats due to change to ruby memory...
2012-10-15 Nilay Vaishruby: improved support for functional accesses
2012-10-15 Nilay Vaishmemtest: move check on outstanding requests
2012-10-15 Nilay Vaish ruby: register multiple memory controllers
2012-10-15 Nilay Vaishruby: remove AbstractMemOrCache
2012-10-15 Nilay Vaishruby: allow function definition in slicc structs
2012-10-15 Nilay Vaishruby banked array: do away with event scheduling
2012-10-15 Nilay Vaishruby: reset timing after cache warm up
2012-10-15 Andreas HanssonMem: Fix incorrect logic in bus blocksize check
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonMem: Separate the host and guest views of memory backin...
2012-10-15 Andreas HanssonCheckpoint: Make system serialize call children
2012-10-15 Andreas HanssonMem: Use deque instead of list for bus retries
2012-10-15 Andreas HanssonFix: Address a few minor issues identified by cppcheck
2012-10-15 Andreas HanssonStats: Update stats for cache timings in cycles
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-10-15 Andreas HanssonStats: Update memtest stats after setting clock
2012-10-15 Andreas HanssonConfigs: Set the memtest clock to a reasonable value
2012-10-15 Andreas HanssonStats: Update stats for new default L1-to-L2 bus clock...
2012-10-15 Andreas HanssonRegression: Use CPU clock and 32-byte width for L1...
2012-10-15 Andreas HanssonStats: Update stats for use of two-level builder
2012-10-15 Andreas HanssonRegression: Use addTwoLevelCacheHierarchy in configs
2012-10-15 Andreas HanssonClock: Inherit the clock from parent by default
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