yosys.git
2020-12-08 David Shahnexus: Add MULTADDSUB9X9WIDE sim model
2020-12-07 David Shahnexus: Add LRAM inference
2020-12-02 David Shahnexus: More efficient CO mapping
2020-12-01 Miodrag MilanovićMerge pull request #2460 from pepijndevos/simple-gowin
2020-11-30 Pepijn de Vosadd -noalu and -json option for apicula
2020-11-26 Yosys BotBump version
2020-11-25 whitequarkMerge pull request #2452 from whitequark/rtlil-remove...
2020-11-25 Miodrag MilanovićMerge pull request #2453 from YosysHQ/mmicko/verilog_as...
2020-11-25 Miodrag MilanovicAdd verilog backend option for simple_lhs
2020-11-25 whitequarkrtlil: remove dotted identifiers.
2020-11-25 Miodrag Milanovicgenerate only simple assignments in verilog backend
2020-11-25 Claire XenMerge pull request #2133 from dh73/nodev_head
2020-11-25 whitequarkMerge pull request #2442 from cr1901/sccache
2020-11-25 whitequarkMerge pull request #2450 from nitz/sim-vcd-filename
2020-11-25 William D.... Makefile: Update ABCREV to bring in sccache fixes.
2020-11-25 Yosys BotBump version
2020-11-24 Chris DaileyAdd rewrite_filename for sim -vcd argument.
2020-11-24 whitequarkMerge pull request #2428 from whitequark/check-processes
2020-11-24 Miodrag MilanovićMerge pull request #2448 from nitz/tcl-script-documenta...
2020-11-24 Miodrag MilanovićMerge pull request #2295 from epfl-vlsc/firrtl_blackbox...
2020-11-24 nitztcl -h message only if YOSYS_ENABLE_TCL defined.
2020-11-23 Sahand KashaniFormatting fixes
2020-11-21 Yosys BotBump version
2020-11-20 Miodrag MilanovićMerge pull request #2443 from YosysHQ/dave/nexus-mult...
2020-11-20 David Shahnexus: DSP inference support
2020-11-19 William D.... Makefile: Add disabled-by-default ENABLE_SCCACHE config...
2020-11-19 Yosys BotBump version
2020-11-18 Miodrag MilanovićMerge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
2020-11-18 David Shahnexus: Add DSP simulation model
2020-11-18 Miodrag MilanovicFix duplicated parameter name typo
2020-11-17 Yosys BotBump version
2020-11-16 William Woodruffbackends/blif: Remove unused vector of strings (#2420)
2020-11-16 Miodrag MilanovićMerge pull request #2438 from kbeckmann/gowin_rpll
2020-11-11 Konrad Beckmannsynth_gowin: Add rPLL blackbox
2020-11-11 Yosys BotBump version
2020-11-10 Miodrag MilanovićMerge pull request #2433 from YosysHQ/paths_as_globals
2020-11-08 Yosys BotBump version
2020-11-07 whitequarkMerge pull request #2414 from zeldin/abc-depend-clang-fix
2020-11-07 Marcus ComstedtPrevent CXXFLAGS from leaking to abc Makefile
2020-11-07 Miodrag MilanovićMerge pull request #2432 from Xiretza/nexus-tests
2020-11-06 Miodrag MilanovicExpose abc and data paths as globals
2020-11-03 whitequarkcheck: add support for processes.
2020-11-03 whitequarkcheck: reformat log/help text to match most other passes
2020-11-03 Yosys BotBump version
2020-11-02 whitequarkMerge pull request #2426 from whitequark/cxxrtl-auto-top
2020-11-02 whitequarkcxxrtl: run `hierarchy -auto-top` if no top module...
2020-11-02 Yosys BotBump version
2020-11-01 whitequarkMerge pull request #2425 from whitequark/cxxrtl-meminit...
2020-11-01 whitequarkcxxrtl: don't assert on non-constant $meminit inputs.
2020-11-01 whitequarkMerge pull request #2424 from whitequark/cxxrtl-multipl...
2020-11-01 whitequarkcxxrtl: don't assert on wires with multiple drivers.
2020-11-01 Yosys BotBump version
2020-10-31 whitequarkMerge pull request #2416 from QuantamHD/master
2020-10-31 Yosys BotBump version
2020-10-30 Miodrag MilanovicUpdate verific version
2020-10-29 XiretzaUpdate nexus arch tests to new harness
2020-10-29 Ethan MahintorabiThis patch adds support for defining the ABC location...
2020-10-25 Yosys BotBump version
2020-10-24 Marcelina Kościelnickaxilinx: Fix attributes_test.ys
2020-10-23 Yosys BotBump version
2020-10-22 David Shahnexus: Add make_transp to BRAMs
2020-10-22 N. EngelhardtMerge pull request #2403 from nakengelhardt/sim_timescale
2020-10-22 Marcelina Kościelnickamemory_dff: Fix needlessly duplicating enable bits.
2020-10-22 Yosys BotBump version
2020-10-21 Marcelina Kościelnickabtor: Use Mem helper.
2020-10-21 Marcelina Kościelnickasmt2: Use Mem helper.
2020-10-21 Marcelina Kościelnickaverilog_backend: Use Mem helper.
2020-10-21 Marcelina Kościelnickasim: Use Mem helper.
2020-10-21 Marcelina Kościelnickaclk2fflogic: Use Mem helper.
2020-10-21 Marcelina Kościelnickaopt_mem: Use Mem helpers.
2020-10-21 Marcelina Kościelnickamemory_bram: Use Mem helpers.
2020-10-21 Marcelina Kościelnickamemory_map: Use Mem helpers.
2020-10-21 Marcelina Kościelnickamemory_unpack: Use Mem helpers.
2020-10-21 Marcelina Kościelnickamemory_collect: Use Mem helpers.
2020-10-21 Marcelina Kościelnickamemory_nordff: Use Mem helpers.
2020-10-21 Marcelina KościelnickaAdd new helper structures to represent memories.
2020-10-21 N. Engelhardtuse strftime instead of put_time for gcc 4.8 compatibility
2020-10-21 Yosys BotBump version
2020-10-20 clairexenMerge pull request #2405 from byuccl/fix_xilinx_cells
2020-10-20 clairexenMerge pull request #2404 from YosysHQ/claire/fixrpcargs
2020-10-20 Yosys BotBump version
2020-10-19 Jeff GoedersMove signal declarations to before first use
2020-10-19 Claire Xenia... Fix argument handling in connect_rpc
2020-10-19 Miodrag MilanovićMerge pull request #2397 from daveshah1/nexus
2020-10-16 N. Engelhardtwild guessing at the problem because it builds fine...
2020-10-16 N. Engelhardtsim -vcd: add date, version, and option for timescale
2020-10-16 Yosys BotBump version
2020-10-15 clairexenMerge pull request #2398 from jakobwenzel/smtbmc-escape
2020-10-15 David Shahsynth_nexus: Initial implementation
2020-10-13 Yosys BotBump version
2020-10-12 Miodrag Milanovicextend verific library API for formal apps and generators
2020-10-09 Yosys BotBump version
2020-10-08 Marcelina Kościelnickaopt_clean: Better memory handling.
2020-10-06 Jakob Wenzelsmtbmc: escape identifiers in verilog testbench
2020-10-06 Yosys BotBump version
2020-10-05 Miodrag MilanovićUpdate required Verific version
2020-10-03 Yosys BotBump version
2020-10-02 clairexenMerge pull request #2396 from YosysHQ/claire/empty...
2020-10-02 Yosys BotBump version
2020-10-01 Claire Xenia... Ignore empty parameters in Verilog module instantiations
next