gem5.git
2008-05-20 Ali SaidiIGbE: Implement sending packet that is contained in... copyright_update
2008-05-20 Stephen HinesSCons: Fixing SCons bug 2006 issues for non-alpha ISAs
2008-05-15 Ali SaidiMake sure that output files are always checked success...
2008-05-06 Ali SaidiSCons: More scons fixing for SCons bug 2006
2008-04-10 Ali SaidiSCons: add comments to SConscript documenting bug worka...
2008-04-10 Ali SaidiPhysicalMemory: Add parameter for variance in memory...
2008-04-08 Ali SaidiSCons: Manually specifying header only directories...
2008-04-08 Ali SaidiSCons: Make BATCH options global sticky so libelf is...
2008-04-08 Ali SaidiSCons: Add check for SCons version since the latest...
2008-03-25 Ali SaidiIGbE: Fix bug that limits wire performance a bit
2008-03-25 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-03-25 Steve ReinhardtFix handling of writeback-induced writebacks in atomic...
2008-03-25 Gabe BlackX86: Put an RTC into the CMOS part of the southbridge.
2008-03-25 Gabe BlackDevices: Separate out the MC146818 RTC so both Alpha...
2008-03-25 Gabe BlackX86: Turn #defines into consts.
2008-03-25 Gabe BlackX86: Start implementing the south bridge stuff.
2008-03-25 Gabe BlackX86: Change the Opteron platform to be the PC platform.
2008-03-24 Steve ReinhardtDelete the Request for a no-response Packet
2008-03-24 Steve ReinhardtDon't FastAlloc MSHRs since we don't allocate them...
2008-03-24 Steve ReinhardtAdd FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct...
2008-03-23 Steve ReinhardtFix cache problem with writes to tempBlock
2008-03-20 Gabe BlackMIPS: Check endianness of binaries in SE mode.
2008-03-18 Steve ReinhardtUpdate long regression stats for semi-recent cache...
2008-03-17 Steve ReinhardtFix a few Packet memory leaks.
2008-03-17 Steve ReinhardtRestructure bus timing calcs to cope with pkt being...
2008-03-15 Steve ReinhardtFix subtle cache bug where read could return stale...
2008-03-16 Ali SaidiSimpoints: Fix regression bug/Don't set process.simpoin...
2008-03-07 Gabe BlackMerge
2008-03-07 Gabe BlackX86: Refine the local APIC.
2008-03-06 Vilas SridharanO3CPU: Don't call dumpInsts if DEBUG is not defined
2008-03-01 Gabe BlackX86: Don't map the local APIC into the physical address...
2008-02-29 Ali SaidiAdded tag m5_2.0_beta4 for changeset cad8c2b5d2ec
2008-02-29 Ali SaidiAdded tag m5_2.0_beta5 for changeset fb826c79a385
2008-02-29 Lisa HsuError out if -s is used without --caches (instead of... m5_2.0_beta5
2008-02-29 Ali SaidiConfigs: Make sure options don't conflict
2008-02-29 Ali SaidiConfigs: Fix some bugs we introduced in the simpoints...
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Steve ReinhardtUpdate outputs for quick tests to reflect fixed cache...
2008-02-27 Korey SewellAdd comments in code to describe bug conditions.
2008-02-27 Korey SewellFix Load/Store Queue squashing after a SMT thread is...
2008-02-27 Korey SewellFix offset in removeThread() function so that float...
2008-02-27 Steve ReinhardtRevamp cache timing access mshr check to make stats...
2008-02-27 Rick StrongConfigs: Make using Simpoints easier with some config...
2008-02-27 Gabe BlackX86: Put in initial implementation of the local APIC.
2008-02-27 Gabe BlackX86: Implement the INVLPG instruction and the TIA microop.
2008-02-27 Gabe BlackTLB: Make a TLB base class and put a virtual demapPage...
2008-02-27 Gabe BlackX86: Get PCI config space to work, and adjust address...
2008-02-27 Steve ReinhardtCache: better comments particularly regarding writeback...
2008-02-26 Ali SaidiUpdate make release, README, and RELEASE_NOTES for b5
2008-02-26 Gabe BlackBus: Update the stats for the recent bus fix.
2008-02-26 Gabe BlackBus: Fix the bus timing to be more realistic.
2008-02-22 Vilas Sridharanadd instruction count fast forwaing and max instruction...
2008-02-19 Stephen HinesAdded ARM_SE as a build option.
2008-02-16 Steve ReinhardtUpdate stats for new writeback behavior.
2008-02-16 Steve ReinhardtMake L2+ caches allocate new block for writeback misses
2008-02-16 Steve ReinhardtUpdate stats for some unknown minor x86 changes
2008-02-14 Ali SaidiCPU: move the PC Events code to a place where the code...
2008-02-14 Ali SaidiConfigs: Change Simulation.py to return a subclass...
2008-02-11 Ali SaidiUpdate copyright dates
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-11 Steve ReinhardtEXTRAS now points to src instead of needing 'src' subdir.
2008-02-11 Steve ReinhardtWait to set BUILD_DIR until *after* env is copied.
2008-02-11 Nicolas ZeaBus: Only update port cache when there is an item to...
2008-02-11 Ali SaidiIGbE: Fix a couple of bugs.
2008-02-10 Steve ReinhardtFix #include lines for renamed cache files.
2008-02-10 Steve ReinhardtRename cache files for brevity and consistency with...
2008-02-06 Stephen HinesMake the Event::description() a const function
2008-02-06 Stephen HinesAdd base ARM code to M5
2008-02-06 Steve ReinhardtCleaned up os.path imports a bit.
2008-02-06 Steve ReinhardtMake EXTRAS work for SConsopts too.
2008-01-23 Gabe BlackX86: Put an SMBios/DMI table in memory.
2008-01-23 Gabe BlackX86: Optomize the bit scanning instruction microassembl...
2008-01-22 Gabe BlackX86: Implement and attach the BSR and BSF instructions.
2008-01-21 Gabe BlackX86: Fill out group17 in the decoder.
2008-01-21 Gabe BlackX86: Use the existing boot_osflags instead of duplicati...
2008-01-16 Ali SaidiUpdate long o3 regressions for o3 change in previous...
2008-01-15 Steve ReinhardtUpdate O3 ref outputs: very minor stats change due...
2008-01-14 Ke MengThe reason is that the event is supposed to put the...
2008-01-12 Gabe BlackX86: Redo the bit test instructions.
2008-01-12 Gabe BlackX86: Fix the wrmsr instruction.
2008-01-12 Gabe BlackX86: Make the effective segment base shadow the regular...
2008-01-12 Gabe BlackX86: Make the IO ports work using extra physical addres...
2008-01-12 Gabe BlackX86: Fix the general IO instructions dataSize.
2008-01-06 Geoffrey BlakeTemporary fix for ll/sc bug see flyspray task for more...
2008-01-02 Steve ReinhardtVery minor memtest regression stats changes from recent...
2008-01-02 Steve ReinhardtAdd ReadRespWithInvalidate to handle multi-level cohere...
2008-01-02 Steve ReinhardtMark cache-to-cache MSHRs as downstreamPending when...
2008-01-02 Steve ReinhardtDon't DPRINTF in the middle of a PrintReq.
2008-01-02 Steve ReinhardtBug fix: functional cache port now needs otherPort...
2008-01-02 Steve ReinhardtAdditional comments and helper functions for PrintReq.
2008-01-02 Steve ReinhardtAdd functional PrintReq command for memory-system debug...
2008-01-02 Steve ReinhardtFix formatting and comments in cache_impl.hh
2008-01-01 Gabe BlackSPARC: Fix a bug where the TLB would match against...
2007-12-18 Ali SaidiCheckpointing: Fix a bug in the simulation script when...
2007-12-16 Ali SaidiCPU: Update where the simple cpus read their cpu id...
2007-12-11 Steve ReinhardtFix minor bug in util/style.py
2007-12-03 Gabe BlackX86: Update the parser reference output which has myste...
2007-12-03 Gabe BlackX86: Please excuse my dear Aunt Sally. (precedence...
2007-12-02 Gabe BlackX86: Make sure the memory index is calculated using...
2007-12-02 Gabe BlackX86: Fix a copy/paste mistake where the bit test instru...
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