yosys.git
2017-02-24 Clifford WolfMerge pull request #320 from joshhead/uninstall-binpath-fix
2017-02-24 Josh HeadapohlAdd missing slashes in paths for make uninstall
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfPreserve string parameters
2017-02-23 Clifford WolfFix mingw compile issue (2nd attempt)
2017-02-23 Clifford WolfFix mingw compile issue (maybe.. I can't test it)
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-22 Clifford WolfUpdate ABC to hg rev 8da4dc435b9f
2017-02-19 Clifford WolfAdd "yosys-smtbmc -S <opt>"
2017-02-16 Clifford WolfCopy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 Clifford WolfFix eval implementation of $_NOR_
2017-02-14 Clifford WolfFix incorrect "incompatible re-declaration of wire...
2017-02-14 Clifford WolfAdd warning about x/z bits left unconnected in EDIF...
2017-02-14 Clifford WolfFix double-call of log_pop() in synth_greenpak4
2017-02-14 Clifford WolfMerge pull request #313 from azidar/bugfix-assign-wmask
2017-02-13 Adam IzraelevitzMore progress on Firrtl backend.
2017-02-13 Clifford WolfDo not fix port widths on any blackbox instances
2017-02-13 Clifford WolfFix techmap for inout ports connected to inout ports
2017-02-12 Clifford WolfDo not eagerly fix port widths on parameterized cells
2017-02-12 Clifford WolfAdd "yosys -w" for suppressing warnings
2017-02-11 Clifford WolfAdd support for verific mem initialization
2017-02-11 Clifford WolfFix another stupid bug in the same line
2017-02-11 Clifford WolfAdd verific support for initialized variables
2017-02-11 Clifford WolfImprove handling of Verific warnings and error messages
2017-02-11 Clifford WolfFix extremely stupid typo
2017-02-11 Clifford WolfAdd log_wire() API
2017-02-11 Clifford WolfFixed some "used uninitialized" warnings in opt_expr
2017-02-11 Clifford WolfEvaluate all the $(shell ...) stuff for CXXFLAGS et...
2017-02-11 Clifford WolfMerge branch 'stv0g-master'
2017-02-11 Clifford WolfMake MacOS Makefile stuff more compact
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-11 Clifford WolfAdd optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 Clifford WolfMerge pull request #308 from C-Elegans/opt_compare_fix_pr
2017-02-10 C-ElegansFix issue #306, "Bug in opt -full"
2017-02-10 Steffen VogelUse pkg-config for linking tcl-tk
2017-02-10 Steffen VogelDont mix Homebrew and MacPorts build options
2017-02-09 Steffen VogelRemove space after backslash
2017-02-09 Steffen VogelApplied fixes from @joshhead (thanks for your effors!)
2017-02-09 Clifford WolfFix handling of init attributes with strange width
2017-02-09 Clifford WolfAdd checker support to verilog front-end
2017-02-09 Clifford WolfAdd "rand" and "rand const" verific support
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support
2017-02-08 Clifford WolfAdd PSL parser mode to verific front-end
2017-02-07 Steffen VogelAdded notes for compilation on OS X
2017-02-07 Steffen VogelFix compilation on OS X in order to support both MacPor...
2017-02-07 Steffen VogelAllow standard tools to be overwritten in make invocation
2017-02-06 Clifford WolfAdd "read_blif -wideports"
2017-02-05 Clifford WolfFix undef propagation bug in $pmux SAT model
2017-02-05 Clifford WolfUpdate ABC to hg rev a2fcd1cc61a6
2017-02-05 Clifford WolfMerge pull request #304 from esden/gsed-darwin
2017-02-05 Piotr Esden... Use -E sed parameter instead of -r.
2017-02-04 Clifford WolfAdd assert check in "yosys-smtbmc -c"
2017-02-04 Clifford WolfImprove yosys-smtbmc cover() support
2017-02-04 Clifford WolfPartially implement cover() support in yosys-smtbmc
2017-02-04 Clifford WolfFurther improve cover() support
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2017-02-04 Clifford WolfAdd assert/assume support to verific front-end
2017-02-01 Clifford WolfUpdate ABC to hg rev fe96921e5d50
2017-02-01 Clifford WolfUpdate ABC scripts to use "&nf" instead of "map"
2017-01-31 Clifford WolfMerge branch 'C-Elegans-opt_compare_pr'
2017-01-31 Clifford WolfFix indenting and log messages in code merged from...
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-31 Steffen Vogeluse Homebrew only if installed
2017-01-31 Clifford WolfImprove opt_rmdff support for $dlatch cells
2017-01-30 C-ElegansRefactor and generalize the comparision optimization
2017-01-30 Clifford WolfAdd "yosys-smtbmc --aig <aim_filename>:<aiw_filename...
2017-01-30 Clifford WolfAdd $ff and $_FF_ support to equiv_simple
2017-01-28 Clifford WolfAdd "yosys-smtbmc --aig-noheader" and AIGER mem init...
2017-01-26 Clifford WolfBe more conservative with merging large cells into...
2017-01-26 Clifford WolfAdd warnings for quickly growing FSM table size in...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-25 Clifford WolfFix RTLIL::Memory::start_offset initialization
2017-01-21 C-ElegansDo not use b.as_int() in calculation of bit set
2017-01-17 Clifford WolfAdd "enum" and "typedef" lexer support
2017-01-16 C-ElegansOptimize compares to powers of 2
2017-01-16 Clifford WolfMerge pull request #293 from thoughtpolice/minor-cleanup
2017-01-15 Austin Seipppasses/hierarchy: delete some dead code
2017-01-15 C-ElegansFix issue #269, optimize signed compare with 0
2017-01-15 Clifford WolfFix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-11 Clifford WolfFix $initstate handling bug in yosys-smtbmc
2017-01-11 Clifford WolfUpdate ABC to hg id f8cadfe3861f
2017-01-08 Clifford WolfUpdated ABC to hg id 38b26a543f1d
2017-01-05 Clifford WolfFixed handling of local memories in functions
2017-01-04 Clifford WolfAdded "check -initdrv"
2017-01-04 Clifford WolfAdded handling of local memories and error for local...
2017-01-04 Clifford WolfImplicitly set "yosys-smtbmc --noprogress" on windows
2017-01-04 Clifford WolfFixed typo in tests/simple/arraycells.v
2017-01-04 Clifford WolfFixed "yosys-smtbmc --noprogress"
2017-01-03 Clifford WolfAdded Verilog $rtoi and $itor support
2017-01-02 Clifford WolfHandle "always 1" like "always -1" in .smtc files
2017-01-01 Clifford WolfAdded cell port resizing to hierarchy pass
2016-12-31 Clifford WolfUpdated ABC to hg id 55cd83f432c0
2016-12-31 Clifford WolfBugfix in RTLIL::SigSpec::remove2()
2016-12-29 Clifford WolfUpdated ABC to hg id 8c6a635f7a20
2016-12-29 Clifford WolfImproved write_json help message
2016-12-26 Clifford WolfUpdated ABC to hg id f591c081d5e7
2016-12-24 Clifford WolfMerge pull request #284 from azonenberg/master
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-23 Clifford WolfSimplified log_spacer() code
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