gram.git
2020-07-17 Jean THOMASLog DRAM commands
2020-07-17 Jean THOMASPut proc_rmdead after proc_mux
2020-07-17 Jean THOMASName each BankMachine instance to improve VCD output
2020-07-17 Jean THOMASFix CRG parameters
2020-07-17 Jean THOMASFix DQS_N errors
2020-07-17 Jean THOMASAdd more read transactions, add checks, ASAP
2020-07-17 Jean THOMASRemove event in ECP5DDRPHY
2020-07-17 Jean THOMASRemove comment
2020-07-16 Jean THOMASUse assertions in simsoc testbench
2020-07-16 Jean THOMASAdd logging and delays to the simulation to make it...
2020-07-16 Jean THOMASTweak yosys script
2020-07-16 Jean THOMASBackport modifications from example's CRG
2020-07-15 Jean THOMASWrite logic equivalences in a clearer way
2020-07-15 Jean THOMASMake Micron model read the mem_init.txt file
2020-07-15 Jean THOMASMake gram simulations faster
2020-07-15 Jean THOMASAdd initial memory content
2020-07-15 Jean THOMASAdd early code for RAM calibration
2020-07-15 Jean THOMASExpose DFII functions to other objects
2020-07-15 Jean THOMASIncrease UART bridge speed in simulation, decrease...
2020-07-15 Jean THOMASLog RAM signals
2020-07-15 Jean THOMASFix code styling
2020-07-15 Jean THOMASRemove arbiter from headless-ecpix5 example
2020-07-15 Jean THOMASUse random values for memtest
2020-07-13 Jean THOMASPer bytes error highlighting
2020-07-13 Jean THOMASMake _AddressSlicer an elaboratable
2020-07-13 Jean THOMASUpdate amount of tests
2020-07-13 Jean THOMASRemove unnecessary arbiter
2020-07-13 Jean THOMASFix timings in libgram
2020-07-13 Jean THOMASReduce POR duration
2020-07-13 Jean THOMASFix gearing and UART speed
2020-07-13 Jean THOMASAdd additional opt+clean and print stats
2020-07-13 Jean THOMASMake full use of the native port
2020-07-13 Jean THOMASFix gearing
2020-07-13 Jean THOMASFix FakePHY bank emulation
2020-07-13 Jean THOMASRemove UnusedElaboratable warning
2020-07-10 Jean THOMASFix memtest tests (missing parenthesis)
2020-07-10 Jean THOMASAdd more memory tests
2020-07-10 Jean THOMASRemove unused files
2020-07-10 Jean THOMASPut every gram component in the dramsync clock domain
2020-07-10 Jean THOMASUse clock freq from platform
2020-07-10 Jean THOMASUse R02 platform file
2020-07-10 Jean THOMASExternalize CRG
2020-07-10 Jean THOMASFix DDR3 module parameter
2020-07-10 Jean THOMASFix code styling
2020-07-10 Jean THOMASAdd a name to timing_checker submodule
2020-07-10 Jean THOMASRework headless client interface
2020-07-10 Jean THOMASImprove simulation output: add names to submodules
2020-07-10 Jean THOMASDon't test for tREFI=1 in RefreshTimer
2020-07-10 Jean THOMASAdd more R/W operations in test_soc
2020-07-10 Jean THOMASAdd script for launching unit tests with fail fast...
2020-07-10 Jean THOMASRemove GTKW files
2020-07-10 Jean THOMASFix formal checks for RefreshTimer
2020-07-10 Jean THOMASFix tests for _AntiStarvation
2020-07-10 Jean THOMASFix code styling
2020-07-10 Jean THOMASRename VCD file output
2020-07-10 Jean THOMASRename tests, add interleaved read/write test
2020-07-10 Jean THOMASImplement a memory in the bank simulator, check for...
2020-07-10 Jean THOMASFix timings in simulation to prevent tDLLK errors
2020-07-10 Jean THOMASAdd POR start/end logging in simsoc testbench
2020-07-09 Jean THOMASMake power-on delay signal synchronous
2020-07-09 Jean THOMASFix formatting in headless example
2020-07-09 Jean THOMASAdd test for SoC readout
2020-07-09 Jean THOMASDisable Assert statements until they are natively suppo...
2020-07-09 Jean THOMASComment buggy assertions
2020-07-09 Jean THOMASAdd imports for Assert & Assume in FakePHY
2020-07-09 Jean THOMASFix counter reset condition bug
2020-07-09 Jean THOMASFix syntax in FakePHY assertions
2020-07-09 Jean THOMASUse assertions as a temporary replacement for Display...
2020-07-09 Jean THOMASRemove unused BitFlip
2020-07-09 Jean THOMASUpdate build script to include software version
2020-07-08 Jean THOMASAdd temporary code for SoC tests with FakePHY
2020-07-08 Jean THOMASPort FakePHY to nMigen
2020-07-08 Jean THOMASMatch ECPIX-5 DRAM parameters in Micron's model
2020-07-08 Jean THOMASImport fake PHY from LiteDRAM (non functionnal ATM)
2020-07-08 Jean THOMASFix styling
2020-07-08 Jean THOMASAdd test case for AntiStarvation
2020-07-08 Jean THOMASFix bugs in _AntiStarvation
2020-07-08 Jean THOMASUpdate memtest code
2020-07-08 Jean THOMASRemove useless variables in _Steerer, ensure command...
2020-07-08 Jean THOMASMake an Elaboratable out of the anti_starvation function
2020-07-08 Jean THOMASAdd links to various docs that have been helpful
2020-07-08 Jean THOMASDrop YoWASP, build Yosys and SymbiYosys from source
2020-07-08 Jean THOMASFix dram_model path in .gitattributes
2020-07-08 Jean THOMASFix clock input
2020-07-08 Jean THOMAScke => clk_en in SoC testbench
2020-07-07 Jean THOMASUpdate cke => clk_en in test
2020-07-07 Jean THOMASFix code styling
2020-07-07 Jean THOMASFix code styling
2020-07-07 Jean THOMASReplace cke with clk_en
2020-07-07 Jean THOMASFix CRG PLL parameters (fixing #23)
2020-07-06 Jean THOMASRename from cke to clk_en
2020-07-06 Jean THOMASMake RefreshTimer fully synchronous (#24)
2020-07-06 Jean THOMASAdd write transactions in the simulation testbench
2020-07-06 Jean THOMASReduce amount of combinatorial statements to improve...
2020-07-06 Jean THOMASFix formal support in FHDLTestCase
2020-07-03 Jean THOMASRemove Diamond install script
2020-07-03 Jean THOMASAdd SourceHut badge
2020-07-03 Jean THOMASAdd .gitattributes file
2020-07-03 Jean THOMASRemove Diamond install as it only comes with models...
2020-07-03 Jean THOMASUse CRG parameters that actually work on hardware
next