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nmigen.git
2019-01-02 William D.... hdl.xfrm: Add Assert and Assume abstract methods for... commit | commitdiff | tree
2019-01-02 William D.... hdl.dsl: Support Assert and Assume where an Assign... commit | commitdiff | tree
2019-01-02 William D.... hdl.ast: Add Assert and Assign statements. commit | commitdiff | tree
2019-01-01 whitequarkhdl.ast: experimentally add Value._as_const. commit | commitdiff | tree
2019-01-01 whitequarkback.rtlil: fix typo. commit | commitdiff | tree
2019-01-01 whitequarkhdl.rec: include record name in error message. commit | commitdiff | tree
2019-01-01 whitequarkhdl.rec: use a helpful error on unknown field reference. commit | commitdiff | tree
2019-01-01 whitequarkhdl.mem: add DummyPort, for testing and verification. commit | commitdiff | tree
2018-12-31 whitequarkback.rtlil: match shape of Array elements to ArrayProxy... commit | commitdiff | tree
2018-12-31 whitequarkback.rtlil: fix typo. commit | commitdiff | tree
2018-12-29 whitequarklib.cdc: fix tests to actually run. commit | commitdiff | tree
2018-12-29 whitequarkback.pysim: warn if simulation is not run. commit | commitdiff | tree
2018-12-28 whitequarkhdl.rec: add basic record support. commit | commitdiff | tree
2018-12-28 whitequarktracer: factor out get_src_loc(). commit | commitdiff | tree
2018-12-27 whitequarklib.coding: fix tests to actually run, and fix code... commit | commitdiff | tree
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing(). commit | commitdiff | tree
2018-12-27 whitequarkhdl.mem: add missing __all__. commit | commitdiff | tree
2018-12-26 Jean-François... compat.genlib.coding: fix import. commit | commitdiff | tree
2018-12-26 whitequarklib.coding: port from Migen. commit | commitdiff | tree
2018-12-26 whitequarklib.cdc: add tests for MultiReg. commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of... commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs. commit | commitdiff | tree
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values... commit | commitdiff | tree
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver). commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: add signal decoder to FSM state signal. commit | commitdiff | tree
2018-12-26 whitequarkhdl.dsl: implement FSM. commit | commitdiff | tree
2018-12-26 whitequarkback.rtlil: clarify $verilog_initial_trigger behavior... commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: unbreak d47c1f8a. commit | commitdiff | tree
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic. commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty... commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: always output negative values as two's... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: emit dummy logic to work around Verilog... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: do not translate empty fragments. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: only translate switch tests once. commit | commitdiff | tree
2018-12-23 whitequarkcli: generate: guess file type from extension. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: fix swapped operands in mux codegen. commit | commitdiff | tree
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA... commit | commitdiff | tree
2018-12-22 whitequarkcompat.genlib.fsm: fix naming for non-Signal LHS. commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: split processes as finely as possible. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: always initialize the entire memory. commit | commitdiff | tree
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce... commit | commitdiff | tree
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory. commit | commitdiff | tree
2018-12-22 whitequarkback.verilog: do not rename internal signals. commit | commitdiff | tree
2018-12-22 whitequarkcompat: fix confusing naming for memory port address... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... commit | commitdiff | tree
2018-12-22 whitequarkcompat: do not finalize native submodules twice. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide verilog.convert shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from... commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide Memory shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct... commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments... commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use different naming for array signals. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add simulation model for memory. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add tests for all error conditions. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa... commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment... commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: explicitly pad constants with zeroes. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: fix translation of Cat. commit | commitdiff | tree
2018-12-20 whitequarkir: allow non-Signals in Instance ports. commit | commitdiff | tree
2018-12-19 whitequarksetup: update pyvcd dependency, for var_type="string". commit | commitdiff | tree
2018-12-18 whitequarkcompat: import genlib.record from Migen. commit | commitdiff | tree
2018-12-18 whitequarkcompat: add wrappers for Slice.stop, Cat.l, _ArrayProxy... commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts} commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: implement *. commit | commitdiff | tree
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: eliminate most dictionary lookups. commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast, hdl.xfrm: various microoptimizations to speed... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: use arrays instead of dicts for signal... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: naming. NFC. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: fix an off-by-1 in add_sync_process(). commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: trigger processes waiting on Tick() exactly... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: continue running simulator processes until... commit | commitdiff | tree
2018-12-18 whitequarkTravis: cache Yosys installation explicitly. commit | commitdiff | tree
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters... commit | commitdiff | tree
2018-12-17 whitequarkTravis: build and cache Yosys. commit | commitdiff | tree
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict. commit | commitdiff | tree
2018-12-17 whitequarkhdl.ast: factor out _MappedKeyDict, _MappedKeySet.... commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: update for Yosys master. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Array. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Part. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: handle reset_less domains. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: add clock domain support. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: cleanup. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: extract _StatementCompiler. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: simplify. NFC. commit | commitdiff | tree
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