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yosys.git
2019-06-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-10
Eddie Hung
Add some more comments
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2019-06-10
David Shah
Merge pull request #1082 from corecode/u4k
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2019-06-10
Simon Schubert
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR...
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2019-06-08
Clifford Wolf
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs
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2019-06-07
Eddie Hung
Fix spacing from spaces to tabs
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2019-06-07
Clifford Wolf
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
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2019-06-07
Eddie Hung
Add read_aiger to CHANGELOG
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2019-06-07
Eddie Hung
Fix spacing (entire file is wrong anyway, will fix...
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2019-06-07
Eddie Hung
Remove unnecessary std::getline() for ASCII
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2019-06-07
Eddie Hung
Test *.aag too, by using *.aig as reference
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2019-06-07
Eddie Hung
Fix read_aiger -- create zero driver, fix init width...
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2019-06-07
Eddie Hung
Use ABC to convert from AIGER to Verilog
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2019-06-07
Eddie Hung
Use ABC to convert AIGER to Verilog, then sat against...
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2019-06-07
Eddie Hung
Add symbols to AIGER test inputs for ABC
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2019-06-07
Eddie Hung
Allow muxcover costs to be changed
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2019-06-07
Clifford Wolf
Merge pull request #1077 from YosysHQ/clifford/pr983
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2019-06-07
Clifford Wolf
Rename implicit_ports.sv test to implicit_ports.v
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2019-06-07
Clifford Wolf
Fixes and cleanups in AST_TECALL handling
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2019-06-07
Clifford Wolf
Merge branch 'pr_elab_sys_tasks' of https://github...
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2019-06-07
Clifford Wolf
Merge branch 'tux3-implicit_named_connection'
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2019-06-07
Clifford Wolf
Merge pull request #1076 from thasti/centos7-build-fix
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2019-06-07
Clifford Wolf
Cleanup tux3-implicit_named_connection
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2019-06-07
Clifford Wolf
Merge branch 'implicit_named_connection' of https:...
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2019-06-07
Stefan Biereigel
remove boost/log/exceptions.hpp from wrapper generator
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2019-06-06
tux3
SystemVerilog support for implicit named port connections
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2019-06-06
Clifford Wolf
Merge pull request #1060 from antmicro/parsing_attr_on_...
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2019-06-06
David Shah
Merge pull request #1073 from whitequark/ecp5-diamond-iob
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2019-06-06
whitequark
ECP5: implement all Diamond I/O buffer primitives.
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2019-06-06
Clifford Wolf
Merge pull request #1071 from YosysHQ/eddie/fix_1070
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2019-06-06
Clifford Wolf
Merge pull request #1072 from YosysHQ/eddie/fix_1069
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2019-06-05
Eddie Hung
Missing doc for -tech xilinx in shregmap
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2019-06-05
Eddie Hung
Error out if no top module given before 'sim'
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2019-06-05
Eddie Hung
Fix typo in opt_rmdff
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2019-06-05
Eddie Hung
Merge pull request #1067 from YosysHQ/clifford/fix1065
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2019-06-05
Maciej Kurc
Fixed memory leak.
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2019-06-05
Clifford Wolf
Merge pull request #1066 from YosysHQ/clifford/fix1056
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2019-06-05
Clifford Wolf
Major rewrite of wire selection in setundef -init
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2019-06-05
Clifford Wolf
Indent fix
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2019-06-05
Clifford Wolf
Merge pull request #999 from jakobwenzel/setundefInitFix
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2019-06-05
Clifford Wolf
Fix typo in fmcombine log message, fixes #1063
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2019-06-05
Clifford Wolf
Suppress driver-driver conflict warning for unknown...
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2019-06-05
Clifford Wolf
Remove yosys_banner() from python wrapper init, fixes...
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2019-06-04
Clifford Wolf
Merge pull request #1062 from tux3/patch-1
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2019-06-04
Tux3
README.md: Missing formatting for <tag>
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2019-06-04
Maciej Kurc
Moved tests that fail with Icarus Verilog to /tests...
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2019-06-04
Eddie Hung
Merge pull request #1061 from YosysHQ/eddie/techmap_and...
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2019-06-04
Eddie Hung
Remove extra newline
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2019-06-04
Eddie Hung
Execute techmap and arith_map simultaneously
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2019-06-03
Maciej Kurc
Added tests for attributes
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2019-06-02
Clifford Wolf
Only support Symbiotic EDA flavored Verific
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2019-05-31
Maciej Kurc
Added support for parsing attributes on port connections.
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2019-05-31
Clifford Wolf
Fix "tee" handling of log_streams
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2019-05-30
Clifford Wolf
Enable Verific flag veri_elaborate_top_level_modules_ha...
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2019-05-30
Clifford Wolf
Merge pull request #1057 from mmicko/fix_478
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2019-05-29
Miodrag Milanovic
Aded one more load of .conf to support change of prefix
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2019-05-28
Clifford Wolf
Merge pull request #1049 from YosysHQ/clifford/fix1047
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2019-05-28
Clifford Wolf
Merge pull request #1050 from YosysHQ/clifford/wandwor
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2019-05-28
Clifford Wolf
Do not use shiftmul peepopt pattern when mul result...
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2019-05-28
Clifford Wolf
Merge pull request #1048 from mmicko/fix_enable_pyosys
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2019-05-28
Clifford Wolf
Refactor hierarchy wand/wor handling
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2019-05-28
Clifford Wolf
Add actual wandwor test that is part of "make test"
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2019-05-28
Clifford Wolf
Merge branch 'wandwor' of https://github.com/thasti...
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2019-05-28
Miodrag Milanovic
Remove info line in 2nd load of conf file
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2019-05-28
Miodrag Milanovic
Moved pyosys block in Makefile
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2019-05-28
Clifford Wolf
Merge pull request #1045 from mmicko/afl-gcc-target
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2019-05-27
Miodrag Milanovic
make config-afl-gcc to help creating conf file
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2019-05-27
Miodrag Milanovic
Added afl-gcc as target for fuzzer
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2019-05-27
Stefan Biereigel
Merge branch 'master' into wandwor
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2019-05-27
Stefan Biereigel
reformat wand/wor test
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2019-05-27
Stefan Biereigel
remove port direction workaround from test case
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2019-05-27
Stefan Biereigel
update README.md with wand/wor information
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2019-05-27
Stefan Biereigel
remove leftovers from ast data structures
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2019-05-27
Stefan Biereigel
move wand/wor resolution into hierarchy pass
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2019-05-27
Clifford Wolf
Merge pull request #1044 from mmicko/invalid_width_range
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2019-05-27
Clifford Wolf
Merge pull request #1043 from mmicko/unsized_constant
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2019-05-27
Clifford Wolf
Merge pull request #1026 from YosysHQ/clifford/fix1023
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2019-05-27
Clifford Wolf
Merge pull request #1030 from Kmanfi/makefile_osx
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2019-05-27
Miodrag Milanovic
Give error instead of asserting for invalid range,...
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2019-05-27
Miodrag Milanovic
Added support for unsized constants, fixes #1022
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2019-05-27
Kaj Tuomi
Guard all Python-api related items.
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2019-05-26
Clifford Wolf
Merge pull request #1035 from YosysHQ/eddie/opt_rmdff
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2019-05-26
Clifford Wolf
Merge pull request #1042 from mmicko/git_ignore_python
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2019-05-26
Miodrag Milanovic
Add files to ignore for python build
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2019-05-25
Eddie Hung
Revert enable check
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2019-05-25
Clifford Wolf
Merge pull request #1041 from YosysHQ/clifford/fix1040
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2019-05-25
Clifford Wolf
Fix handling of offset and upto module ports in write_b...
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2019-05-25
Eddie Hung
Fix init
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2019-05-25
Eddie Hung
Fix typos
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2019-05-25
Eddie Hung
Add more tests
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2019-05-25
Eddie Hung
Call proc
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2019-05-25
Eddie Hung
opt_rmdff to optimise even in presence of enable signal...
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2019-05-25
Eddie Hung
Fix duplicate driver
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2019-05-24
Eddie Hung
Add comments
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2019-05-24
Eddie Hung
Resolve @cliffordwolf review, set even if !has_init
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2019-05-24
Clifford Wolf
Add proper error message for btor recursion_guard
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2019-05-23
Eddie Hung
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
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2019-05-23
Eddie Hung
Fix spacing
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2019-05-23
Eddie Hung
Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23
Eddie Hung
Add opt_rmdff tests
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