gem5.git
2014-05-09 Andrew Bardsleyarm: Add branch flags onto macroops
2014-05-09 Andrew Bardsleycpu: Allow setWhen on trace objects
2014-05-09 Curtis Dunhamarm: add preliminary ISA splits for ARM arch
2014-05-09 Curtis Dunhamarch: teach ISA parser how to split code across files
2014-05-09 Geoffrey Blakeconfig: Avoid generating a reference to myself for...
2014-05-09 Geoffrey Blakearch, arm: Preserve TLB bootUncacheability when switchi...
2014-05-09 Curtis Dunhamcpu: add more instruction mix statistics
2014-05-09 Mitch Hayengamem: Squash prefetch requests from downstream caches
2014-05-09 Stephan Diestelhorststats: Method stats source
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-05-09 Sascha Bischoffmem: Auto-generate CommMonitor trace file names
2014-05-09 Geoffrey Blakearm: Panics in miscreg read functions can be tripped...
2014-05-09 Chris Emmonsdev: Set HDLCD default pixel clock for 1080p @ 60Hz
2014-05-09 Matt Evansarm: quick hack to allow a greater number of CPUs to...
2014-05-09 Eric Van Hensbergenarm: Add Makefile for aarch64 build of util/m5
2014-05-09 Curtis Dunhamarch: remove inline specifiers on all inst constrs...
2014-05-09 Curtis Dunhamarm: cleanup ARM ISA definition
2014-03-20 Curtis Dunhamext: disable PLY debugging
2014-05-09 Curtis Dunhamscons: Require SWIG >= 2.0.4 and remove vector typemaps
2014-04-23 Curtis Dunhamarm: Correctly display disassembly of vldmia/vstmia
2014-04-23 Mitch Hayengautil: Valgrind suppression addition
2014-04-23 Andreas Hanssonsim: Use correct unit for abort message
2014-04-23 Mitchell Hayengacpu: Fix setTranslateLatency() bug for squashed instruc...
2014-04-23 Sascha Bischoffmisc: Proper type check and import for PortRef
2014-04-01 Mitch Hayengacpu: Fix case where o3 lsq could print out uninitialize...
2014-04-01 Mitch Hayengamem: Don't print out the data of a cache block
2014-04-23 Mitchell Hayengaarm: Don't use a stack allocated mnemonic
2014-04-23 Dam Sunwoocpu: Add O3 CPU width checks
2014-04-23 Curtis Dunhambase: explicitly suggest potential use of 'All' debug...
2014-04-23 Curtis Dunhamarch: remove 'null update' check in isa-parser
2014-02-11 Curtis Dunhamstats: better error message for uninitialized statistic
2014-04-22 Andreas Hanssonstats: updates for pc-switcheroo-full due to o3 smt fix
2014-04-19 Nilay Vaishstats: updates due to o3 smt fix
2014-04-19 Nilay Vaishruby: slicc: remove old documentation
2014-04-19 Nilay Vaishruby: slicc: slight change to rule for transitions
2014-04-19 Faissal Sleimano3: Fix occupancy checks for SMT
2014-04-19 Marco Elverruby: recorder: Fix (de-)serializing with different...
2014-04-19 Nilay Vaishconfig: ruby: remove memory controller from network...
2014-04-14 Anthony Gutierrezarm: set default kernels for VExpress_EMM and VExpress_...
2014-04-13 Andreas Hanssonscons: Fix python-config parsing by adding strip()
2014-04-10 Gedare Bloomconfig: add num-work-ids command line option
2014-04-10 Stian Hvatumscons: compile on systems where python2 and python3...
2014-04-09 Andreas Sandbergkvm, x86: Add initial support for multicore simulation
2014-04-09 Andreas Sandbergdev: Protect PollEvent processing when running in paral...
2014-04-08 Nilay Vaishruby: slicc: change enqueue statement
2014-04-08 Nilay Vaishruby: coherence protocols: drop the phrase IntraChip
2014-04-03 Andreas Sandbergsim: Add the ability to lock and migrate between event...
2014-04-01 Anthony Gutierrezext: add McPAT source
2014-04-01 Anthony Gutierrezarm: fix typos in makefile for ARM m5 util and link...
2014-04-01 Nilay Vaishconfigs: use SimpleMemory when using ruby in se mode
2014-03-25 Marco Elvercpu: o3: lsq: Fix TSO implementation
2014-03-23 Andreas Hanssonstats: Update stats for DRAM changes
2014-03-23 Andreas Hanssonmem: Track DRAM read/write switching and add hysteresis
2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl
2014-03-23 Andreas Hanssonmem: Change memory defaults to be more representative
2014-03-23 Wendy Elsassermem: Add close adaptive paging policy to DRAM controlle...
2014-03-23 Andreas Hanssonmem: DRAM controller tidying up
2014-03-23 Andreas Hanssonmem: Fix bug in DRAM bytes per activate
2014-03-23 Andreas Hanssonmem: Limit the accesses to a page before forcing a...
2014-03-23 Andreas Hanssonmem: Make DRAM write queue draining more aggressive
2014-03-23 Andreas Hanssonconfig: Add a DRAM efficiency-sweep script
2014-03-23 Neha Agarwalcpu: DRAM Traffic Generator
2014-03-23 Neha Agarwalmem: DDR3 config for comparing with DRAMSim2
2014-03-23 Andreas Hanssonmem: More descriptive address-mapping scheme names
2014-03-23 Curtis Dunhamscons: Shush scons
2014-03-23 Stan Czerniawskimisc: Fix -q (quiet) flag
2014-03-23 Andreas Hanssonruby: Move Ruby debug flags to ruby dir and remove...
2014-03-23 Andreas Hanssonutil: Add support for detection of gzipped packet traces
2014-03-23 Andreas Hanssonmem: Include the DRAMSim2 wrapper in NULL build
2014-03-23 Andreas Hanssonext: Fix typo in DRAMSim2 SConscript
2014-03-23 Sascha Bischoffmem: CommMonitor trace warn on non-timing mode
2014-03-23 Stan Czerniawskicpu: Add basic check to TrafficGen initial state
2014-03-23 Andrew Bardsleydev: Fix IsaFake's cxx_header setting
2014-03-23 Eric Van Hensbergenarm: m5ops readfile64 args broken, offset coming throug...
2014-03-23 Andreas Hanssonbase: Fix error message time unit (cycle -> tick)
2014-03-20 Nilay Vaishstats: updates due to changes to ruby config scripts
2014-03-20 Nilay Vaishruby: consumer: avoid accessing wakeup times when waking up
2014-03-20 Nilay Vaishruby: garnet: convert network interfaces into clocked...
2014-03-20 Nilay Vaishruby: slicc: code refactor
2014-03-20 Nilay Vaishconfig: ruby: rename _cpu_ruby_ports to _cpu_ports
2014-03-20 Nilay Vaishconfig: fs.py: move creating of test/drive systems...
2014-03-20 Nilay Vaishconfig: remove ruby_fs.py
2014-03-20 Nilay Vaishruby: no piobus in se mode
2014-03-17 Nilay Vaishconfig: ruby: remove piobus from protocols
2014-03-17 Nilay Vaishruby: remove some of the unnecessary code
2014-03-16 Andreas Sandbergkvm: Clean up signal handling
2014-03-16 Andreas Sandbergkvm: x86: Adjust PC to remove the CS segment base address
2014-03-16 Andreas Sandbergkvm: x86: Add support for x86 INIT and STARTUP handling
2014-03-12 Paul Rosenfeldalpha: Small removal of dead comments/code from alpha ISA
2014-03-07 Andreas Hanssoncpu: Make CPU and ThreadContext getters const
2014-03-07 Geoffrey Blakearm: Handle functional TLB walks properly
2014-03-07 Prakash Ramrakhyanimem: Fix incorrect assert failure in the Cache
2014-03-07 Radhika Jagtapmem: Edit proto Packet and enhance the python script
2014-03-07 Mitch Hayengascons: Fix clang version identification for OSX
2014-03-07 Stephan Diestelhorstmisc: Add panic_if / fatal_if / chatty_assert
2014-03-07 Mitch Hayengascons: Fixes uninitialized warnings issued by clang
2014-03-07 Stephan Diestelhorstarm: Fix uninitialised warning with gcc 4.8
2014-03-07 Ali Saidimem: Wakeup sleeping CPUs without caches on LLSC
2014-03-06 Andreas Sandbergsim: Schedule the global sync event at curTick() +...
2014-03-03 Andreas Sandbergx86: Setup correct TSL/TR segment attributes on INIT
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