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yosys.git
2019-09-30
Eddie Hung
Cleanup $currQ from aigerparse
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2019-09-30
Eddie Hung
Remove need for $currQ port connection
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2019-09-30
Eddie Hung
Add explanation to abc_map.v
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2019-09-30
Eddie Hung
Cleanup
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2019-09-30
Eddie Hung
Add comment
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2019-09-30
Eddie Hung
Use a cell_cache to instantiate once rather than opt_me...
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2019-09-30
Eddie Hung
scc call on active module module only, plus cleanup
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2019-09-30
Eddie Hung
Use derived module
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
Eddie Hung
Update doc for equiv_opt
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2019-09-30
whitequark
Merge pull request #1406 from whitequark/connect_rpc
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2019-09-30
Eddie Hung
Merge pull request #1397 from btut/fix/python_wrappers_...
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2019-09-30
whitequark
rpc: new frontend.
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2019-09-30
whitequark
libs: import json11.
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2019-09-30
Miodrag Milanović
Merge pull request #1416 from YosysHQ/mmicko/frontend_b...
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2019-09-30
Clifford Wolf
Bump version
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2019-09-30
Clifford Wolf
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_a...
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2019-09-30
Clifford Wolf
Merge pull request #1417 from YosysHQ/clifford/fixasync...
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2019-09-30
Clifford Wolf
Fix $dlatch handling in async2sync
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2019-09-30
Eddie Hung
Add latch test modified from #1363
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2019-09-30
Eddie Hung
Add LDCE/LDPE sim library, remove from *cells_xtra...
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2019-09-30
Marcin Kościelnicki
synth_xilinx: Support latches, remove used-up FF init...
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2019-09-30
Eddie Hung
Missing endmodule
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2019-09-30
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-30
Eddie Hung
Merge pull request #1414 from hzeller/improve-replace...
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2019-09-29
Eddie Hung
Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29
Eddie Hung
FDCE_1 does not have IS_CLR_INVERTED
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2019-09-29
Eddie Hung
Fix "scc" call inside abc9 to consider all wires
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2019-09-29
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-29
Miodrag Milanovic
Fix reading aig files on windows
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2019-09-29
Miodrag Milanovic
Open aig frontend as binary file
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2019-09-29
Miodrag Milanović
Merge pull request #1413 from YosysHQ/mmicko/backend_bi...
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2019-09-29
Clifford Wolf
Merge pull request #1411 from aman-goel/YosysHQ-master
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2019-09-29
Henner Zeller
Avoid work in replace() if rules empty.
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2019-09-29
Eddie Hung
Big rework; flop info now mostly in cells_sim.v
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2019-09-28
Miodrag Milanovic
Add aiger and protobuf backends binary support
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2019-09-28
Miodrag Milanovic
Support binary files for backends, fixes #1407
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2019-09-28
Eddie Hung
Fix box name
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2019-09-28
Eddie Hung
Use abc_mergeability attr for "r" extension
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2019-09-28
Eddie Hung
Split ABC9 based on clocking only, add "abc_mergeabilit...
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2019-09-28
Eddie Hung
Fix infinite recursion
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2019-09-28
Eddie Hung
Add -select option to aigmap
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2019-09-28
Eddie Hung
Fix typo
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2019-09-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-27
Eddie Hung
Re-order
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2019-09-27
Eddie Hung
Missing (* mul2dsp *) for sliceB
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2019-09-27
Eddie Hung
equiv_opt to call async2sync when not -multiclock like...
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2019-09-27
Eddie Hung
Ooops AREG and BREG to default to -1
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2019-09-27
Aman Goel
Corrects btor2 backend
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2019-09-27
Marcin Kościelnicki
Fix _TECHMAP_REMOVEINIT_ handling.
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-27
Miodrag Milanović
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt...
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2019-09-27
Miodrag Milanovic
Change order of parameters, to work on other os
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2019-09-27
Clifford Wolf
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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2019-09-26
Eddie Hung
Update doc with max cascade chain of 20
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2019-09-26
Eddie Hung
Do not always zero out C (e.g. during cascade breaks)
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2019-09-26
Eddie Hung
Update doc
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2019-09-26
Eddie Hung
Zero out ports
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2019-09-26
Eddie Hung
xilinx_dsp_cascade to also cascade AREG and BREG
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2019-09-26
Eddie Hung
Try recursive pmgen for P cascade
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2019-09-26
Eddie Hung
Missing an '&'
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2019-09-26
Eddie Hung
Combine 'flatten' & 'coarse' labels in synth_ecp5 so...
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2019-09-26
Miodrag Milanovic
Make read/write gzip files on macos works, fixes #1357
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2019-09-26
Eddie Hung
Typo
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2019-09-26
Eddie Hung
CREG to check for \keep
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2019-09-26
Eddie Hung
Remove newline
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2019-09-26
Eddie Hung
select once
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2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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2019-09-26
Eddie Hung
mul2dsp.v slice names
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2019-09-26
Eddie Hung
Do not die if DSP48E1.P has no users (would otherwise...
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2019-09-26
Eddie Hung
Reject if (* init *) present
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2019-09-26
Eddie Hung
Remove unnecessary check for A_SIGNED != B_SIGNED;...
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2019-09-26
Eddie Hung
Revert "Remove _TECHMAP_CELLTYPE_ check since all ...
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2019-09-26
Eddie Hung
Revert "No need for $__mul anymore?"
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2019-09-26
Eddie Hung
Rework xilinx_dsp postAdd for new wreduce call
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2019-09-26
Eddie Hung
Only wreduce on t:$add
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2019-09-25
Eddie Hung
Remove _TECHMAP_CELLTYPE_ check since all $mul
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2019-09-25
Eddie Hung
Fix memory issue since SigSpec& could be invalidated
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2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegty...
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2019-09-25
Eddie Hung
No need for $__mul anymore?
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2019-09-25
Eddie Hung
unextend only used in init
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2019-09-25
Eddie Hung
Call 'wreduce' after mul2dsp to avoid unextend()
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2019-09-25
Eddie Hung
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
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2019-09-25
SergeyDegtyar
Change sync controls to async.
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2019-09-25
Clifford Wolf
Merge pull request #1402 from YosysHQ/clifford/portlist
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2019-09-25
Clifford Wolf
Improve "portlist" command
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2019-09-24
Clifford Wolf
Add "portlist" command
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2019-09-24
SergeyDegtyar
adffs test update (equiv_opt -multiclock).
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2019-09-24
Eddie Hung
Add (* techmap_autopurge *) to abc_unmap.v too
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2019-09-24
Eddie Hung
"abc_padding" attr for blackbox outputs that were padde...
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2019-09-24
Eddie Hung
Force $inout.out ports to begin with '$' to indicate...
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2019-09-24
Eddie Hung
Add techmap_autopurge to outputs in abc_map.v too
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2019-09-24
Eddie Hung
Revert "Add a xilinx_finalise pass"
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2019-09-24
Eddie Hung
Revert "Remove (* techmap_autopurge *) from abc_unmap...
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2019-09-24
Eddie Hung
Revert "Vivado does not like zero width port connections"
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2019-09-24
Eddie Hung
Vivado does not like zero width port connections
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2019-09-24
Eddie Hung
Remove (* techmap_autopurge *) from abc_unmap.v since...
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2019-09-24
Eddie Hung
Add a xilinx_finalise pass
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2019-09-23
Eddie Hung
Set [AB]CASCREG to legal values
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2019-09-23
Eddie Hung
Comment to explain separating CREG packing
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