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nmigen.git
2018-12-15 whitequarkfhdl.ir: test iter_comb(), iter_sync() and iter_signals(). commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ir: fix incorrect uses of positive to say non... commit | commitdiff | tree
2018-12-15 whitequarkcompat.fhdl.structure: handle If/Elif with multi-bit... commit | commitdiff | tree
2018-12-14 whitequarkcompat.fhdl.module: allow adding native submodules... commit | commitdiff | tree
2018-12-14 whitequarkFix deprecations in Python 3.7. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: preserve process locations through add_sync... commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ast: clean up stub error messages. NFC. commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ir: automatically flatten hierarchy to resolve... commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ir: Fragment.{drive→add_driver} commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: count delta cycles separately to avoid... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: simplify. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: revert 70ebc6f2. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: fix implicit boolean conversion. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: squash one level of hierarchy. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: implement blocking assignment semantics... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: undriven sync signals should return to... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: in simulator sync processes, start by waiti... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: make initial phase configurable. commit | commitdiff | tree
2018-12-14 whitequarkcompat.sim: match clock period. commit | commitdiff | tree
2018-12-14 whitequarkcompat: add run_simulation shim. commit | commitdiff | tree
2018-12-14 whitequarkpysim.back: fix add_sync_process wrapper to handle... commit | commitdiff | tree
2018-12-14 whitequarkcompat.fhdl.module: fix specials. commit | commitdiff | tree
2018-12-14 whitequarkcompat: add fhdl.specials.TSTriple shim. commit | commitdiff | tree
2018-12-14 whitequarkgenlib.io: import TSTriple from Migen. commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ast: fix Switch with constant test. commit | commitdiff | tree
2018-12-14 whitequarkcompat: add genlib.cdc.MultiReg shim. commit | commitdiff | tree
2018-12-14 whitequarkcompat.fhdl.module: update deprecation messages. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: Simulator({gtkw_signals→traces}=). commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: better naming. NFC. commit | commitdiff | tree
2018-12-14 whitequarkTravis: install pyvcd. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: implement most operators and add tests. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: close .vcd/.gtkw files on context manager... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: show more legible names for processes in... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: throw exceptions back at processes. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: add gtkw traces even more robustly. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: accept (and evaluate) generator functions. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: skip VCD signal population if VCD is not... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: allow processes to evaluate expressions. commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ir: oops, we defined DomainError twice. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: more general clean-up. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: general clean-up. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: accept any valid assignments from processes. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: robustly retrieve vcd names for clk/rst... commit | commitdiff | tree
2018-12-14 whitequarkfhdl.xfrm: implement DomainLowerer. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: undriven comb signals should return to... commit | commitdiff | tree
2018-12-14 whitequarkast, back.pysim: allow specifying user-defined decoders... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: fix completely broken codegen for Switch. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: raise an exception if delta cycles blow... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: if requested, write a gtkw file with a... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: explain how delta cycles work. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: delay clock processes by one half period. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: implement "sync processes", like migen... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: allow suspending processes until a tick... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: use bare ints for signal values (-5% runtime). commit | commitdiff | tree
2018-12-14 whitequarksetup: add missing import. commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: collect handlers before running (-5% runtime). commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: allow multiple registered handlers per... commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: fix handling of process termination. commit | commitdiff | tree
2018-12-13 whitequarkback.pysim: new simulator backend (WIP). commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: rename ClockDomain signals together with domain. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: move Fragment prepare logic from back.rtlil. commit | commitdiff | tree
2018-12-13 whitequarkback.verilog: remove debug code. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: record port direction explicitly. commit | commitdiff | tree
2018-12-13 whitequarkcompat.genlib.fsm: import/wrap Migen code. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: a subfragment's input that we don't drive... commit | commitdiff | tree
2018-12-13 whitequarkfhdl, back: trace and emit source locations of values. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: never give subfragment cells names starting... commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: don't crash propagataing ports in empty fragments. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: remove iter_domains(). commit | commitdiff | tree
2018-12-13 whitequarkfhdl: cd_name→domain. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: add tests. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: implement DomainRenamer. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: add test for ControlInserter with subfragments. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.xfrm: add tests for ResetInserter, CEInserter. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: add tests for port propagation. commit | commitdiff | tree
2018-12-13 whitequarkSet up Travis CI. commit | commitdiff | tree
2018-12-13 whitequarkAdd LICENSE. commit | commitdiff | tree
2018-12-13 whitequarksetup: check Python version. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for lowering. 99% branch coverage. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.cd: rename ClockDomain.{reset→rst}. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for submodules. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level... commit | commitdiff | tree
2018-12-13 whitequarkfhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: fix Switch._?hs_signals() for switch without... commit | commitdiff | tree
2018-12-13 whitequarkback.verilog: detect undriven public wires using Yosys. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: fix swapped operands in sync assign. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explicitly set the top module. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: explain how port enumeration works. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: explain how RTLIL conversion works. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear... commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: give clocks and resets nicer names. commit | commitdiff | tree
2018-12-13 whitequarkcompat.fhdl.module: implement finalization. commit | commitdiff | tree
2018-12-13 whitequarkback.rtlil: match shape of $mux ports A/B/Y. commit | commitdiff | tree
2018-12-13 whitequarktracer: add support for Python 3.7. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: bits_sign→shape. commit | commitdiff | tree
2018-12-13 whitequarkfhdl.ast: add tests for most logic. commit | commitdiff | tree
2018-12-13 whitequarkMeasure test coverage. commit | commitdiff | tree
2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code... commit | commitdiff | tree
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