yosys.git
2015-11-08 Clifford WolfMerge pull request #97 from zeldin/master
2015-11-08 Marcus ComstedtFix a segfault in dffinit when the value has too few...
2015-11-07 Clifford WolfAdded "singleton" pass
2015-11-06 Clifford WolfFixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
2015-11-05 Clifford WolfBugfix in mapping $tribuf to $_TBUF_
2015-10-31 Clifford WolfBugfix in memory_dff
2015-10-31 Clifford WolfImprovements in wreduce
2015-10-30 Clifford WolfBugfix in Xilinx LUT mapping
2015-10-28 Clifford WolfImproved SigMap performance
2015-10-27 Clifford WolfImprovements in new SigMap
2015-10-27 Clifford WolfUse mfp<> in equiv_mark
2015-10-27 Clifford WolfRemoved old SigMap implementation
2015-10-27 Clifford WolfAdded hashlib::mfp and new SigMap
2015-10-25 Clifford WolfImprovements in equiv_struct
2015-10-25 Clifford WolfMajor refactoring of equiv_struct
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-10-25 Clifford WolfAdded "equiv_add -cell"
2015-10-25 Clifford Wolfequiv_struct now creates equiv_merged attributes
2015-10-24 Clifford WolfImprovements in equiv_struct
2015-10-24 Clifford Wolfrenamed SigSpec::to_single_sigbit() to SigSpec::as_bit...
2015-10-24 Clifford Wolfimprovement in "stat"
2015-10-24 Clifford WolfFixed driver conflict handling (various cmds)
2015-10-24 Clifford Wolfequiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 Clifford WolfFixed handling of driver-driver conflicts in wreduce
2015-10-23 Clifford WolfAdded equiv_mark command
2015-10-23 Clifford WolfDisabled "Skipping blackbox module" msg in show command
2015-10-23 Clifford WolfAdded support for ":" as comment symbol after ;-parsing
2015-10-23 Clifford WolfAlso merge $equiv cells in equiv_struct
2015-10-23 Clifford WolfImprovements in equiv_struct
2015-10-22 Clifford WolfAdded equiv_purge
2015-10-21 Clifford WolfAdded equiv_struct command
2015-10-21 Clifford WolfImproved inout handling in equiv_make
2015-10-20 Clifford WolfProgress on cell help messages
2015-10-17 Clifford WolfProgress on cell help messages
2015-10-15 Clifford WolfProgress in yosys-smtbmc
2015-10-15 Clifford WolfFixed bug in verilog parser
2015-10-15 Clifford WolfImprovements in yosys-smtbmc
2015-10-15 Clifford WolfBugfixes in handling of "keep" attribute on wires
2015-10-14 Clifford WolfMore "yosys-smtbmc -c" fixes
2015-10-14 Clifford WolfFixed yosys-smtbmc -c
2015-10-14 Clifford WolfAdded "prep" command
2015-10-14 Clifford WolfAdded more cell descriptions
2015-10-14 Clifford WolfAdded first help messages for cell types
2015-10-13 Clifford WolfAdded yosys-smtbmc copyright
2015-10-13 Clifford WolfImprovements in yosys-smtbmc
2015-10-13 Clifford WolfAdded yosys-smtbmc
2015-10-13 Clifford WolfImplemented smtbmc.py -i
2015-10-13 Clifford WolfAdded smtbmc.py
2015-10-13 Clifford WolfAdded write_smt2 -wires
2015-10-13 Clifford WolfAdded examples/ top-level directory
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-10-13 Clifford WolfMerge branch 'master' of https://github.com/rubund...
2015-10-13 Clifford WolfFixed "flatten" for unconnected inout ports
2015-10-10 Ruben UndheimUse DESTDIR as defined in https://gnu.org/prep/standard...
2015-10-10 Ruben UndheimUse LDFLAGS, CXXFLAGS and CPPFLAGS from the environment...
2015-10-07 Clifford WolfAdded support for "parameter" and "localparam" in globa...
2015-10-01 Clifford WolfFixed complexity of assigning to vectors in constant...
2015-09-30 Clifford WolfFixed detection of unconditional $readmem[hb]
2015-09-27 Clifford WolfAdded edgetypes command
2015-09-26 Clifford WolfSome cleanups in qwp
2015-09-25 Clifford WolfAdded "test_cell -noeval"
2015-09-25 Clifford WolfAdded wreduce $mul support and fixed signed $mul opt_co...
2015-09-25 Clifford WolfBugfix in bram read-enable code
2015-09-25 Clifford WolfBugfixes in $readmem[hb]
2015-09-25 Clifford WolfBugfixes in writing of memories as Verilog
2015-09-25 Clifford WolfFixed segfault in AstNode::asReal
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-09-24 Clifford WolfAdded pivoting to qwp solver
2015-09-24 Clifford WolfImproved qwp performance
2015-09-24 Clifford WolfAdded statistics summary to "qwp"
2015-09-24 Clifford WolfFixed memory_bram for ROMs in BRAMs with write-enable...
2015-09-24 Clifford WolfFixed AstNode::mkconst_bits() segfault on zero-sized...
2015-09-23 Clifford WolfAdded read_verilog -nodpi
2015-09-23 Clifford WolfBugfix in handling of multi-dimensional memories
2015-09-23 Clifford WolfWarning for $display/$write outside initial block
2015-09-23 Clifford WolfFixed support for $write system task
2015-09-22 Clifford WolfFixed detection of "task foo(bar);" syntax error
2015-09-22 Clifford WolfFixed multi-level prefix resolving
2015-09-22 Clifford WolfFixed segfault on invalid verilog constant 1'b_
2015-09-21 Clifford WolfFixed emcc build
2015-09-21 Clifford WolfDo not detect fsm state registers with init attribute
2015-09-21 Clifford WolfBugfix in "qwp" pass
2015-09-20 Clifford WolfImprovements and fixes in "qwp" pass
2015-09-20 Clifford WolfAdded "qwp -dump"
2015-09-20 Clifford WolfAdded "qwp" command
2015-09-19 Andrew ZonenbergImprovements to $display system task
2015-09-18 Clifford WolfAdded nlutmap
2015-09-18 Clifford WolfAdded lut2mux pass
2015-09-18 Clifford WolfCosmetic fix in Module::addLut()
2015-09-18 Clifford WolfAdded buffer detection to "abc -lut"
2015-09-18 Clifford WolfRenamed GreenPAK4 cells, improved GP4 DFF mapping
2015-09-18 Clifford WolfAdded support for "dfflibmap -liberty +/..."
2015-09-18 Clifford WolfAdded detection of "mux inverter" chains in opt_const
2015-09-18 Clifford WolfAdded $logic_not handling to fsm_detect
2015-09-18 Clifford WolfAdded $finish and $display to README
2015-09-18 Clifford WolfMerge branch 'feat-finish-disp'
2015-09-18 Clifford WolfAdded AST_INITIAL checks for $finish and $display
2015-09-18 Andrew ZonenbergInitial implementation of $display()
2015-09-18 Andrew ZonenbergInitial implementation of $finish()
2015-09-16 Clifford WolfFixed copy&paste typo in synth_greenpak4
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