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yosys.git
2021-08-14
Marcelina Kościelnicka
proc_prune: Make assign removal and promotion per-bit...
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2021-08-14
github-actions...
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2021-08-13
Rupert Swarbrick
Generate an RTLIL representation of bind constructs
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2021-08-13
Marcelina Kościelnicka
Add opt_mem_widen pass.
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2021-08-13
Marcelina Kościelnicka
memory_share: Add -nosat and -nowiden options.
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2021-08-13
Marcelina Kościelnicka
memory_dff: Recognize soft transparency logic.
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2021-08-13
Marcelina Kościelnicka
Add new opt_mem_priority pass.
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2021-08-13
Miodrag Milanović
Merge pull request #2932 from YosysHQ/mwk/logger-check...
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2021-08-13
Brett Witherspoon
sv: improve support for wire and var with user-defined...
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2021-08-13
github-actions...
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2021-08-12
Marcelina Kościelnicka
memory_share: Pass addresses through sigmap_xmux everyw...
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2021-08-12
Marcelina Kościelnicka
logger: Add -check-expected subcommand.
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2021-08-12
github-actions...
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2021-08-11
Marcelina Kościelnicka
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
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2021-08-11
Marcelina Kościelnicka
memory_dff: Recognize read ports with reset / initial...
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2021-08-11
Marcelina Kościelnicka
proc_memwr: Use the v2 memwr cell.
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2021-08-11
Marcelina Kościelnicka
Add v2 memory cells.
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2021-08-11
github-actions...
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2021-08-10
Marcelina Kościelnicka
kernel/mem: Introduce transparency masks.
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2021-08-10
Michael Singer
Allow optional comma after last entry in enum
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2021-08-10
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2021-08-09
Marcelina Kościelnicka
Refactor common parts of SAT-using optimizations into...
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2021-08-08
github-actions...
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2021-08-07
Marcelina Kościelnicka
opt_merge: Use FfInitVals.
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2021-08-07
github-actions...
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2021-08-06
Marcelina Kościelnicka
verilog: Support tri/triand/trior wire types.
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2021-08-05
github-actions...
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2021-08-04
Marcelina Kościelnicka
memory_share: Don't skip ports with EN wired to input...
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2021-08-04
github-actions...
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2021-08-03
Marcelina Kościelnicka
memory_bram: Move init data swizzling before other...
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2021-08-03
github-actions...
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2021-08-02
Miodrag Milanovic
Require latest verific
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2021-08-02
github-actions...
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2021-08-01
Marcelina Kościelnicka
backend/verilog: Add alternate mode for transparent...
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2021-08-01
Marcelina Kościelnicka
memory_bram: Some refactoring
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2021-07-31
github-actions...
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2021-07-30
Miodrag Milanović
Update version.yml
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2021-07-30
Maciej Dudek
Fixes xc7 BRAM36s
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2021-07-30
Zachary Snow
proc_rmdead: use explicit pattern set when there are...
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2021-07-30
Zachary Snow
genrtlil: add width detection for AST_PREFIX nodes
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2021-07-30
github-actions...
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2021-07-29
Marcelina Kościelnicka
opt_lut: Allow more than one -dlogic per cell type.
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2021-07-29
Zachary Snow
verilog: save and restore overwritten macro arguments
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2021-07-29
github-actions...
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2021-07-28
Marcelina Kościelnicka
verilog: Emit $meminit_v2 cell.
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2021-07-28
Marcelina Kościelnicka
backends/verilog: Support meminit with mask.
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2021-07-28
Marcelina Kościelnicka
memory: Introduce $meminit_v2 cell, with EN input.
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2021-07-28
github-actions...
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2021-07-27
Marcelina Kościelnicka
proc: Run opt_expr at the end
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2021-07-27
Marcelina Kościelnicka
opt_expr: Propagate constants to port connections.
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2021-07-27
github-actions...
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2021-07-26
Miodrag Milanovic
Add version bump workflow
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2021-07-21
Miodrag Milanovic
Update to latest verific
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2021-07-20
Rupert Swarbrick
Use new read_id_num helper function elsewhere in hierar...
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2021-07-20
Rupert Swarbrick
Extract connection checking logic from expand_module...
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2021-07-20
whitequark
Merge pull request #2885 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
Merge pull request #2884 from whitequark/cxxrtl-fix...
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2021-07-20
whitequark
cxxrtl: treat wires with multiple defs as not inlinable.
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2021-07-20
whitequark
cxxrtl: treat assignable internal wires used only for...
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2021-07-20
whitequark
Merge pull request #2881 from whitequark/cxxrtl-sideway...
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2021-07-19
whitequark
cxxrtl: escape colon in variable names in VCD writer.
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2021-07-18
whitequark
Merge pull request #2880 from whitequark/cxxrtl-fix...
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2021-07-18
whitequark
cxxrtl: add debug_item::{get,set}.
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2021-07-17
whitequark
Merge pull request #2879 from whitequark/cxxrtl-fix...
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2021-07-17
whitequark
cxxrtl: treat internal wires used only for debug as...
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2021-07-16
Rupert Swarbrick
Add support for parsing the SystemVerilog 'bind' construct
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2021-07-16
whitequark
Merge pull request #2874 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
Merge pull request #2873 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
Merge pull request #2872 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
cxxrtl: run hierarchy pass regardless of (*top*) attrib...
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2021-07-16
whitequark
cxxrtl: emit debug items for unused public wires.
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2021-07-16
whitequark
cxxrtl: don't expect user cell inputs to be wires.
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2021-07-16
whitequark
Merge pull request #2871 from whitequark/cxxrtl-fix...
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2021-07-16
whitequark
cxxrtl: don't mark buffered internal wires as UNUSED...
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2021-07-16
whitequark
Merge pull request #2870 from whitequark/cxxrtl-fix...
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2021-07-15
whitequark
cxxrtl: mark dead local wires as unused even with inlin...
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2021-07-15
Zachary Snow
sv: fix two struct access bugs
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2021-07-15
Rupert Swarbrick
Add a test for interfaces on modules loaded on-demand
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2021-07-15
Rupert Swarbrick
Extract missing module support in hierarchy.cc to a...
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2021-07-14
whitequark
Merge pull request #2866 from rswarbrick/found-init
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2021-07-14
Rupert Swarbrick
Delete unused found_init variable
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2021-07-13
Marcelina Kościelnicka
kernel/mem: Add a coalesce_inits helper.
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2021-07-12
GCHQDeveloper560
Add support for the Bitwuzla solver
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Use delayed removal for inits as well.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Add documentation for more helper functions.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Support memory writes in processes.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Add support for memory read port reset.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Add support for mem read port initial data.
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2021-07-12
Marcelina Kościelnicka
cxxrtl: Convert to Mem helpers.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Commit new values of attributes in emit.
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2021-07-12
Marcelina Kościelnicka
kernel/mem: Make the Mem helpers inherit from AttrObject.
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2021-07-11
Marcelina Kościelnicka
rtlil: Make Process handling more uniform with Cell...
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2021-07-10
Marcelina Kościelnicka
ice40: Fix LUT input indices in opt_lut -dlogic (again).
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2021-07-09
Miodrag Milanovic
Update to latest Verific with extensions for initial...
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2021-07-06
Zachary Snow
sv: fix a few struct and enum memory leaks
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2021-07-06
gatecat
ecp5: Add DCSC blackbox
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2021-07-05
Claire Xen
Merge pull request #2835 from YosysHQ/verific_command
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2021-07-05
Xiretza
Makefile: allow running multiple sanitizers at once
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2021-07-05
Xiretza
Makefile: use git/make -C instead of cd
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2021-07-05
Xiretza
Makefile: pass PRETTY=0 to ABC
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