yosys.git
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
2019-11-23 Eddie HungDo not use log_signal() for empty SigSpec to prevent...
2019-11-23 Eddie HungCall submod once, more meaningful submod names, ignore...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungRemove redundant flatten
2019-11-23 Eddie Hungsubmod to bitty rather bussy, for bussy wires used...
2019-11-23 Eddie HungStray dump
2019-11-23 Eddie HungMove clkpart into passes/hierarchy
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungConstant driven signals are also an input to submodules
2019-11-23 Eddie HungAdd another test with constant driver
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungOops
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungOnly action if there is more than one clock domain
2019-11-23 Eddie HungReplace TODO
2019-11-23 Eddie HungAdd testcase for signal used as part input part output
2019-11-23 Eddie Hungwrite_xaiger back to working with whole modules only
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungCleanup spacing
2019-11-23 Eddie Hungsigmap(wire) should inherit port_output status of POs
2019-11-23 Eddie HungAdd testcase
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungBrackets
2019-11-22 Eddie HungEntry in Makefile.inc
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungAdd to CHANGELOG
2019-11-22 Eddie HungNew 'clkpart' to {,un}partition design according to...
2019-11-22 Eddie HungRevert "write_xaiger to not use module POs but only...
2019-11-22 Eddie HungMissing endmodule
2019-11-22 Clifford WolfMerge pull request #1517 from YosysHQ/clifford/optmem
2019-11-22 Clifford WolfMerge pull request #1515 from YosysHQ/clifford/svastuff
2019-11-22 Clifford WolfAdd "opt_mem" pass
2019-11-22 Clifford WolfAdd Verific support for SVA nexttime properties
2019-11-22 Clifford WolfImprove handling of verific primitives in "verific...
2019-11-22 Clifford WolfAdd Verific SVA support for "always" properties
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-22 David ShahUpdate CHANGELOG and README
2019-11-22 Eddie HungAnother sloppy mistake!
2019-11-22 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-11-22 Eddie Hungasync2sync -> clk2fflogic
2019-11-22 Eddie Hungwrite_xaiger to not use module POs but only write outpu...
2019-11-22 Eddie HungWhen expanding upwards, do not capture $__ABC9_{FF...
2019-11-22 Eddie HungMerge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-22 Eddie HungAdd test
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-21 David Shahproc_dlatch: Add error handling for incorrect always_...
2019-11-21 David Shahsv: Correct parsing of always_comb, always_ff and alway...
2019-11-20 Eddie HungConsistent log message, ignore 's' extension
2019-11-20 Eddie Hungendomain -> ctrldomain
2019-11-20 Eddie HungAdd blackbox model for $__ABC9_FF_ so that clock partit...
2019-11-20 Eddie HungAdd multi clock test
2019-11-20 Eddie HungFix INIT values
2019-11-20 Clifford WolfMerge pull request #1507 from YosysHQ/clifford/verificfixes
2019-11-20 Clifford WolfCorrectly treat empty modules as blackboxes in Verific
2019-11-20 Clifford WolfDo not rename VHDL entities to "entity(impl)" when...
2019-11-20 Eddie HungAdd a equiv test too
2019-11-20 Eddie HungAdd two tests
2019-11-20 Eddie Hungabc9 to support async flops $_DFF_[NP][NP][01]_
2019-11-20 Eddie HungDo not drop async control signals in abc_map.v
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Pepijn de VosRemove dff init altogether
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-18 whitequarkwrite_verilog: add -extmem option, to write split memor...
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names
2019-11-14 David Shahwreduce: Don't trim zeros or sext when not matching...
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'makaimann-label-bads-btor'
2019-11-14 Clifford WolfUse cell name for btor bad state props when it is a...
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-13 Clifford WolfMerge pull request #1486 from YosysHQ/clifford/fsmdetectfix
2019-11-12 Clifford WolfUpdate fsm_detect bugfix
2019-11-12 Clifford WolfBugfix in fsm_detect
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-12 Makai MannAdd an info string symbol for bad states in btor backend
2019-11-12 whitequarkflowmap: when doing mincut, ensure source is always...
2019-11-11 whitequarkflowmap: don't break if that creates a k+2 (and larger...
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Miodrag MilanovicFixed tests
2019-11-11 Clifford WolfDo not map $eq and $ne in cmp2lut, only proper arithmet...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-07 Clifford WolfAdd check for valid macro names in macro definitions
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