2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/clkpart... |
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2019-11-23 |
Eddie Hung | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys... |
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2019-11-23 |
Eddie Hung | Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff |
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2019-11-23 |
Eddie Hung | Do not use log_signal() for empty SigSpec to prevent... |
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2019-11-23 |
Eddie Hung | Call submod once, more meaningful submod names, ignore... |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/clkpart... |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/submod_po... |
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2019-11-23 |
Eddie Hung | Remove redundant flatten |
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2019-11-23 |
Eddie Hung | submod to bitty rather bussy, for bussy wires used... |
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2019-11-23 |
Eddie Hung | Stray dump |
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2019-11-23 |
Eddie Hung | Move clkpart into passes/hierarchy |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/submod_po... |
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2019-11-23 |
Eddie Hung | Constant driven signals are also an input to submodules |
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2019-11-23 |
Eddie Hung | Add another test with constant driver |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/submod_po... |
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2019-11-23 |
Eddie Hung | Oops |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/clkpart... |
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2019-11-23 |
Eddie Hung | Only action if there is more than one clock domain |
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2019-11-23 |
Eddie Hung | Replace TODO |
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2019-11-23 |
Eddie Hung | Add testcase for signal used as part input part output |
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2019-11-23 |
Eddie Hung | write_xaiger back to working with whole modules only |
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2019-11-23 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/submod_po... |
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2019-11-23 |
Eddie Hung | Cleanup spacing |
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2019-11-23 |
Eddie Hung | sigmap(wire) should inherit port_output status of POs |
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2019-11-23 |
Eddie Hung | Add testcase |
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2019-11-22 |
Eddie Hung | Merge branch 'eddie/clkpart' into xaig_dff |
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2019-11-22 |
Eddie Hung | Brackets |
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2019-11-22 |
Eddie Hung | Entry in Makefile.inc |
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2019-11-22 |
Eddie Hung | Merge branch 'eddie/clkpart' into xaig_dff |
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2019-11-22 |
Eddie Hung | Add to CHANGELOG |
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2019-11-22 |
Eddie Hung | New 'clkpart' to {,un}partition design according to... |
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2019-11-22 |
Eddie Hung | Revert "write_xaiger to not use module POs but only... |
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2019-11-22 |
Eddie Hung | Missing endmodule |
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2019-11-22 |
Clifford Wolf | Merge pull request #1517 from YosysHQ/clifford/optmem |
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2019-11-22 |
Clifford Wolf | Merge pull request #1515 from YosysHQ/clifford/svastuff |
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2019-11-22 |
Clifford Wolf | Add "opt_mem" pass |
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2019-11-22 |
Clifford Wolf | Add Verific support for SVA nexttime properties |
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2019-11-22 |
Clifford Wolf | Improve handling of verific primitives in "verific... |
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2019-11-22 |
Clifford Wolf | Add Verific SVA support for "always" properties |
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2019-11-22 |
Clifford Wolf | Merge pull request #1511 from YosysHQ/dave/always |
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2019-11-22 |
Marcin Kościelnicki | gowin: Remove show command from tests. |
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2019-11-22 |
Marcin Kościelnicki | gowin: Add missing .gitignore entries |
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2019-11-22 |
David Shah | Update CHANGELOG and README |
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2019-11-22 |
Eddie Hung | Another sloppy mistake! |
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2019-11-22 |
Eddie Hung | Merge remote-tracking branch 'origin/xaig_dff' into... |
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2019-11-22 |
Eddie Hung | async2sync -> clk2fflogic |
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2019-11-22 |
Eddie Hung | write_xaiger to not use module POs but only write outpu... |
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2019-11-22 |
Eddie Hung | When expanding upwards, do not capture $__ABC9_{FF... |
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2019-11-22 |
Eddie Hung | Merge branch 'eddie/xaig_dff_adff' into xaig_dff |
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2019-11-22 |
Eddie Hung | Add test |
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2019-11-21 |
David Shah | sv: Add tests for SV always types |
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2019-11-21 |
David Shah | proc_dlatch: Add error handling for incorrect always_... |
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2019-11-21 |
David Shah | sv: Correct parsing of always_comb, always_ff and alway... |
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2019-11-20 |
Eddie Hung | Consistent log message, ignore 's' extension |
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2019-11-20 |
Eddie Hung | endomain -> ctrldomain |
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2019-11-20 |
Eddie Hung | Add blackbox model for $__ABC9_FF_ so that clock partit... |
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2019-11-20 |
Eddie Hung | Add multi clock test |
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2019-11-20 |
Eddie Hung | Fix INIT values |
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2019-11-20 |
Clifford Wolf | Merge pull request #1507 from YosysHQ/clifford/verificfixes |
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2019-11-20 |
Clifford Wolf | Correctly treat empty modules as blackboxes in Verific |
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2019-11-20 |
Clifford Wolf | Do not rename VHDL entities to "entity(impl)" when... |
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2019-11-20 |
Eddie Hung | Add a equiv test too |
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2019-11-20 |
Eddie Hung | Add two tests |
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2019-11-20 |
Eddie Hung | abc9 to support async flops $_DFF_[NP][NP][01]_ |
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2019-11-20 |
Eddie Hung | Do not drop async control signals in abc_map.v |
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2019-11-19 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
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2019-11-19 |
Clifford Wolf | Merge pull request #1449 from pepijndevos/gowin |
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2019-11-19 |
Pepijn de Vos | Remove dff init altogether |
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2019-11-19 |
Marcin Kościelnicki | Fix #1462, #1480. |
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2019-11-19 |
Marcin Kościelnicki | xilinx: Add simulation models for MULT18X18* and DSP48A*. |
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2019-11-18 |
Pepijn de Vos | add help for nowidelut and abc9 options |
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2019-11-18 |
Clifford Wolf | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix |
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2019-11-18 |
whitequark | Merge pull request #1494 from whitequark/write_verilog... |
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2019-11-18 |
Marcin Kościelnicki | Fix #1496. |
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2019-11-18 |
whitequark | write_verilog: add -extmem option, to write split memor... |
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2019-11-17 |
Clifford Wolf | Merge pull request #1492 from YosysHQ/dave/wreduce... |
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2019-11-16 |
Pepijn de Vos | Merge branch 'master' of https://github.com/YosysHQ... |
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2019-11-15 |
David Shah | ecp5: Use new autoname pass for better cell/net names |
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2019-11-14 |
David Shah | wreduce: Don't trim zeros or sext when not matching... |
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2019-11-14 |
Clifford Wolf | Merge pull request #1490 from YosysHQ/clifford/autoname |
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2019-11-14 |
Clifford Wolf | Merge pull request #1444 from btut/feature/python_wrapp... |
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2019-11-14 |
Clifford Wolf | Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim |
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2019-11-14 |
Clifford Wolf | Merge branch 'makaimann-label-bads-btor' |
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2019-11-14 |
Clifford Wolf | Use cell name for btor bad state props when it is a... |
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2019-11-14 |
Clifford Wolf | Merge branch 'label-bads-btor' of https://github.com... |
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2019-11-13 |
Clifford Wolf | Add "autoname" pass and use it in "synth_ice40" |
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2019-11-13 |
whitequark | Merge pull request #1488 from whitequark/flowmap-fixes |
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2019-11-13 |
Clifford Wolf | Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix |
commit | commitdiff | tree |
2019-11-12 |
Clifford Wolf | Update fsm_detect bugfix |
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2019-11-12 |
Clifford Wolf | Bugfix in fsm_detect |
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2019-11-12 |
Clifford Wolf | Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne |
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2019-11-12 |
Makai Mann | Add an info string symbol for bad states in btor backend |
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2019-11-12 |
whitequark | flowmap: when doing mincut, ensure source is always... |
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2019-11-11 |
whitequark | flowmap: don't break if that creates a k+2 (and larger... |
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2019-11-11 |
Pepijn de Vos | fix fsm test with proper clock enable polarity |
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2019-11-11 |
Pepijn de Vos | Merge branch 'master' of https://github.com/YosysHQ... |
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2019-11-11 |
Miodrag Milanovic | Fixed tests |
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2019-11-11 |
Clifford Wolf | Do not map $eq and $ne in cmp2lut, only proper arithmet... |
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2019-11-10 |
Clifford Wolf | Merge pull request #1470 from YosysHQ/clifford/subpassdoc |
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2019-11-07 |
Clifford Wolf | Add check for valid macro names in macro definitions |
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