nmigen.git
2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion.
2018-12-13 whitequarkback.rtlil: explicitly set the top module.
2018-12-13 whitequarkfhdl.ir: explain how port enumeration works.
2018-12-13 whitequarkback.rtlil: explain how RTLIL conversion works.
2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear...
2018-12-13 whitequarkback.rtlil: give clocks and resets nicer names.
2018-12-13 whitequarkcompat.fhdl.module: implement finalization.
2018-12-13 whitequarkback.rtlil: match shape of $mux ports A/B/Y.
2018-12-13 whitequarktracer: add support for Python 3.7.
2018-12-13 whitequarkfhdl.ast: bits_sign→shape.
2018-12-13 whitequarkfhdl.ast: add tests for most logic.
2018-12-13 whitequarkMeasure test coverage.
2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code...
2018-12-12 whitequarkcompat.fhdl.bitcontainer: import/wrap Migen code.
2018-12-12 whitequarkfhdl.ast.Signal: implement .like().
2018-12-12 whitequarkfhdl.ir: fix port threading code.
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
2018-12-12 whitequarkfhdl.ast.Signal: fix typo.
2018-12-12 whitequarkfhdl.ast.Signal: implement attrs field.
2018-12-12 whitequarkgenlib.cdc.MultiReg: self.regs should be a private...
2018-12-12 whitequarkfhdl.ast.Signal: implement width derivation from min...
2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen.
2018-12-12 whitequarkfhdl.ast.Signal: implement reset_less signals.
2018-12-12 whitequarkfhdl.ast.Signal: assign an internal name if tracer...
2018-12-12 whitequarkfhdl.dsl: allow f.sync["dom"] as a synonym of f.sync...
2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInse...
2018-12-12 whitequarkInitial commit.