yosys.git
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-16 Eddie HungRe-enable partsel.v test
2019-04-16 Eddie Hungabc9 to call "setundef -zero" behaving as for abc
2019-04-16 Eddie HungNULL check before use
2019-04-16 Eddie HungWIP for box support
2019-04-16 Eddie HungABC to read_box before reading netlist
2019-04-16 Eddie HungMake cells.box whiteboxes not blackboxes
2019-04-16 Eddie Hungread_verilog cells_box.v before techmap
2019-04-16 Eddie Hungsynth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 Eddie HungAdd +/xilinx/cells_box.v containing models for ABC...
2019-04-16 Eddie HungFor 'stat' do not count modules with abc_box_id
2019-04-16 Eddie HungDo not call abc on modules with abc_box_id attr
2019-04-16 Eddie HungRevert "Add abc_box_id attribute to MUXF7/F8 cells"
2019-04-16 Eddie HungUse abc_box_id
2019-04-16 Eddie HungCheck abc_box_id attr
2019-04-16 Eddie HungAdd abc_box_id attribute to MUXF7/F8 cells
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungMerge pull request #937 from YosysHQ/revert-932-eddie...
2019-04-16 Eddie HungRevert "Recognise default entry in case even if all...
2019-04-15 Eddie HungMerge pull request #936 from YosysHQ/README-fix-quotes
2019-04-15 whitequarkREADME: fix some incorrect quoting.
2019-04-13 Eddie HungForgot backslashes
2019-04-13 Eddie HungHandle __dummy_o__ and __const[01]__ in read_aiger...
2019-04-13 Eddie Hungabc to ignore __dummy_o__ and __const[01]__ when re...
2019-04-13 Eddie HungOutput __const0__ and __const1__ CIs
2019-04-13 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-13 Eddie HungFix inout handling for -map option
2019-04-12 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungUse -map instead of -symbols for aiger
2019-04-12 Eddie Hungci_bits and co_bits now a list, order is important...
2019-04-12 Eddie HungAlso cope with duplicated CIs
2019-04-12 Eddie HungWIP
2019-04-12 Eddie HungComment out
2019-04-12 Eddie HungAdd support for synth_xilinx -abc9 and ignore abc9...
2019-04-12 Eddie HungCope with an output having same name as an input (i...
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungMerge pull request #928 from litghost/add_xc7_sim_models
2019-04-12 Eddie HungPI before CI
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-04-12 Keith RothmanRemove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 Clifford WolfMerge pull request #933 from dh73/master
2019-04-12 Clifford WolfMerge pull request #932 from YosysHQ/eddie/fixdlatch
2019-04-12 DiegoFixing issues in CycloneV cell sim
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungMore unused
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungRemove unused
2019-04-11 Eddie HungFixes
2019-04-11 Eddie HungWIP
2019-04-11 Eddie HungSpelling fixes
2019-04-11 Eddie HungAdd default entry to testcase
2019-04-11 Eddie HungRecognise default entry in case even if all cases cover...
2019-04-11 Eddie HungFix cells_map.v some more
2019-04-11 Eddie HungMore fine tuning
2019-04-11 Eddie HungFix cells_map.v
2019-04-11 Eddie HungFix typo
2019-04-11 Eddie HungJuggle opt calls in synth_xilinx
2019-04-11 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-11 Eddie HungAdd non-input bits driven by unrecognised cells as...
2019-04-11 Eddie HungWIP for cells_map.v -- maybe working?
2019-04-10 Eddie HungTry splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 Eddie HungFix for when B_SIGNED = 1
2019-04-10 Eddie HungUpdate doc for synth_xilinx
2019-04-10 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-10 Eddie Hungparse_aiger() to rename all $lut cells after "clean"
2019-04-10 Eddie Hungff_map.v after abc
2019-04-10 Eddie HungTidy up
2019-04-10 Eddie HungMove map_cells to before map_luts
2019-04-10 Eddie HungWIP for $shiftx to wide mux
2019-04-10 Eddie HungUpdate LUT delays
2019-04-09 Eddie HungAdd cells.lut to techlibs/xilinx/
2019-04-09 Eddie Hungsynth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 Eddie HungAdd delays to cells.box
2019-04-09 Eddie HungAdd "-lut <file>" support to abc9
2019-04-09 Keith RothmanFix LUT6_2 definition.
2019-04-09 Eddie Hungsynth_xilinx with abc9 to use -box
2019-04-09 Eddie HungAdd techlibs/xilinx/cells.box
2019-04-09 Eddie HungAdd "-box" option to abc9
2019-04-09 Eddie HungAdd 'setundef -zero' call prior to aigmap in abc9
2019-04-09 Eddie HungComment out
2019-04-09 Eddie HungAdd support for synth_xilinx -abc9 and ignore abc9...
2019-04-09 Keith RothmanAdd additional cells sim models for core 7-series prima...
2019-04-08 Eddie HungFix a few typos
2019-04-08 Eddie HungMore space fixing
2019-04-08 Eddie HungFix spacing
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-08 Clifford WolfMerge pull request #919 from YosysHQ/multiport_transp
2019-04-07 David Shahmemory_bram: Fix multiport make_transp
2019-04-05 Clifford WolfAdd "read_ilang -lib"
2019-04-04 Clifford WolfAdded missing argument checking to "mutate" command
2019-04-03 Eddie HungMerge pull request #913 from smunaut/fix_proc_mux
2019-04-03 Sylvain Munautproc_mux: Fix crash when trying to optimize non-existan...
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates
2019-04-02 David Shahmemory_bram: Consider read enable for address expansion...
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog...
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
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