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yosys.git
2017-06-26
Robert Ou
coolrunner2: Remove debug prints
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2017-06-26
Robert Ou
coolrunner2: Correctly handle $_NOT_ after $sop
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2017-06-26
Robert Ou
coolrunner2: Also construct the XOR cell in the macrocell
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2017-06-26
Robert Ou
coolrunner2: Initial techmapping for $sop
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2017-06-24
Robert Ou
coolrunner2: Initial commit
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2017-06-07
Clifford Wolf
Fix generation of vlogtb output in yosys-smtbmc for...
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2017-06-01
Clifford Wolf
Fix handling of Verilog ~& and ~| operators
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2017-05-31
Clifford Wolf
Update ABC to hg rev efbf7f13ea9e
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2017-05-31
Clifford Wolf
Add dff2ff.v techmap file
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2017-05-30
Clifford Wolf
Fix AIGER back-end for multiple symbols per input/latch...
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2017-05-28
Clifford Wolf
Add "setundef -anyseq"
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2017-05-28
Clifford Wolf
Improve write_aiger handling of unconnected nets and...
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2017-05-27
Clifford Wolf
Change default smt2 solver to yices (Yices 2 has switch...
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2017-05-24
Clifford Wolf
Add aliases for common sets of gate types to "abc -g"
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2017-05-23
Clifford Wolf
Add examples/osu035
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2017-05-23
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-05-23
Clifford Wolf
Merge pull request #346 from azonenberg/master
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2017-05-23
Andrew Zonenberg
greenpak4_counters: Added support for parallel output...
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2017-05-17
Clifford Wolf
Add workaround for CBMC bug to SimpleC back-end
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2017-05-17
Clifford Wolf
Enable readline and tcl in mxe builds
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2017-05-17
Clifford Wolf
Add missing AndnotGate() and OrnotGate() declarations...
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2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
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2017-05-16
Clifford Wolf
Add <modname>_init() function generator to simpleC...
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2017-05-16
Clifford Wolf
Improve simplec back-end
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2017-05-15
Clifford Wolf
Improve simplec back-end
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2017-05-14
Clifford Wolf
Improve simplec back-end
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2017-05-13
Clifford Wolf
Improve simplec back-end
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2017-05-12
Clifford Wolf
Improve simplec back-end
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2017-05-12
Clifford Wolf
Added support for more gate types to simplec back-end
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2017-05-12
Clifford Wolf
Add first draft of simple C back-end
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2017-05-11
Clifford Wolf
Update ABC to hg rev e79576e10d72
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2017-05-08
Clifford Wolf
Fix boolector support in yosys-smtbmc
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2017-04-30
Clifford Wolf
Add support for localparam in module header
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2017-04-28
Clifford Wolf
Fix equiv_simple, old behavior now available with ...
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2017-04-26
Clifford Wolf
Add support for `resetall compiler directive
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2017-04-12
Clifford Wolf
Replace CRLF line endings with LF in de2i.qsf (quartus...
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2017-04-12
Larry Doolittle
Squelch trailing whitespace
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2017-04-07
Clifford Wolf
Add MAX10 and Cyclone IV items to CHANGELOG
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2017-04-07
Clifford Wolf
Merge pull request #337 from dh73/master
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2017-04-06
dh73
Add initial support for both MAX10 and Cyclone IV ...
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2017-04-05
Clifford Wolf
Add ConstEval defaultval feature
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2017-04-05
Clifford Wolf
Fix gcc compiler warning
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2017-03-28
Clifford Wolf
Add front-end detection for *.tcl files
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2017-03-27
Clifford Wolf
Add minisat 00_PATCH_typofixes.patch
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2017-03-27
Clifford Wolf
Remove use of <fpu_control.h> in minisat
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2017-03-20
Clifford Wolf
Add "write_smt2 -stdt" mode
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2017-03-19
Clifford Wolf
Add generation of logic cells to EDIF back-end runtest.py
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2017-03-19
Clifford Wolf
Fix EDIF: portRef member 0 is always the MSB bit
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2017-03-18
Clifford Wolf
Add simple EDIF test case generator and checker
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2017-03-14
Clifford Wolf
Fix verilog pre-processor for multi-level relative...
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2017-03-04
Clifford Wolf
Improve smt2 encodings of assert/assume/cover, better...
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2017-03-02
Clifford Wolf
Add write_aiger $anyseq support
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2017-03-01
Clifford Wolf
Allow $anyconst, etc. in non-formal SV mode
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2017-02-28
Clifford Wolf
Disable opt_merge for $anyseq and $anyconst
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2017-02-28
Clifford Wolf
Use hex addresses in smtbmc vcd mem traces
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2017-02-27
Clifford Wolf
Add "chformal -assert2assume" and friends
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2017-02-27
Clifford Wolf
Add "chformal" pass
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2017-02-26
Clifford Wolf
Add smtbmc support for memory vcd dumping
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2017-02-26
Clifford Wolf
Fix extra newline bug in write_smt2
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2017-02-26
Clifford Wolf
Fix bug in smtio unroll code
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2017-02-26
Clifford Wolf
Fix assert checking in "yosys-smtbmc -c --append"
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2017-02-26
Clifford Wolf
Improve (and fix for stbv mode) SMT2 memory API
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2017-02-25
Clifford Wolf
Add support for "yosys-smtbmc -c --append"
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2017-02-25
Clifford Wolf
Update ABC to hg rev 3a95bfa55df7
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2017-02-25
Clifford Wolf
Merge branch 'klammerj-master'
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2017-02-25
Clifford Wolf
Improve "write_edif" help message
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2017-02-25
Clifford Wolf
Move EdifNames out of double-private namespace
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2017-02-25
Clifford Wolf
Clean up edif code, swap bit indexing of "upto" ports
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair support to AIGER back-end.
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-24
Clifford Wolf
Merge pull request #322 from azonenberg/master
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2017-02-24
Clifford Wolf
Add "write_smt2 -stbv"
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2017-02-24
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-24
Clifford Wolf
Add SMT2 statebv mode (inactive for now)
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2017-02-24
Johann Klammer
Did as you requested, /but/...
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2017-02-24
Clifford Wolf
Merge pull request #320 from joshhead/uninstall-binpath-fix
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2017-02-24
Josh Headapohl
Add missing slashes in paths for make uninstall
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2017-02-23
Johann Klammer
add options for edif flavors
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2017-02-23
Clifford Wolf
Add support for SystemVerilog unique, unique0, and...
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2017-02-23
Clifford Wolf
Preserve string parameters
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2017-02-23
Clifford Wolf
Fix mingw compile issue (2nd attempt)
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2017-02-23
Clifford Wolf
Fix mingw compile issue (maybe.. I can't test it)
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2017-02-23
Clifford Wolf
Added SystemVerilog support for ++ and --
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2017-02-22
Clifford Wolf
Update ABC to hg rev 8da4dc435b9f
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2017-02-19
Clifford Wolf
Add "yosys-smtbmc -S <opt>"
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2017-02-16
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-16
Clifford Wolf
Copy attributes to _TECHMAP_REPLACE_ cells
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2017-02-16
Clifford Wolf
Fix eval implementation of $_NOR_
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2017-02-14
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-14
Clifford Wolf
Fix incorrect "incompatible re-declaration of wire...
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2017-02-14
Clifford Wolf
Add warning about x/z bits left unconnected in EDIF...
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2017-02-14
Clifford Wolf
Fix double-call of log_pop() in synth_greenpak4
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2017-02-14
Clifford Wolf
Merge pull request #313 from azidar/bugfix-assign-wmask
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2017-02-13
Adam Izraelevitz
More progress on Firrtl backend.
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2017-02-13
Clifford Wolf
Do not fix port widths on any blackbox instances
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2017-02-13
Clifford Wolf
Fix techmap for inout ports connected to inout ports
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2017-02-12
Clifford Wolf
Do not eagerly fix port widths on parameterized cells
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2017-02-12
Clifford Wolf
Add "yosys -w" for suppressing warnings
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