Refine memory support to deal with general Verilog memory definitions.
[yosys.git] / backends / firrtl /
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-rw-r--r-- 20 .gitignore
-rw-r--r-- 35 Makefile.inc
-rw-r--r-- 35254 firrtl.cc
-rw-r--r-- 395 test.sh
-rw-r--r-- 1794 test.v