Correct settings for experiment10_verilog & FreePDK45.
[soclayout.git] / experiments10_verilog / freepdk_c4m45 /
drwxr-xr-x   ..
-rwxr-xr-x 1007 Makefile
lrwxrwxrwx 9 add.py -> ../add.py
-rwxr-xr-x 811 build_full.sh
drwxr-xr-x - coriolis2
-rw-r--r-- 1736 design-flow.mk
-rw-r--r-- 4852 doDesign.py
-rwxr-xr-x 1166 mksym.sh
-rw-r--r-- 80 netlists.txt