build/microsemi/libero_soc: only associate timings constraint to timing check (otherw...
[litex.git] / litex / build /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
drwxr-xr-x - altera
-rw-r--r-- 12288 generic_platform.py
-rw-r--r-- 1182 generic_programmer.py
drwxr-xr-x - lattice
drwxr-xr-x - microsemi
-rw-r--r-- 924 openocd.py
drwxr-xr-x - sim
-rw-r--r-- 2502 tools.py
drwxr-xr-x - xilinx