build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
[litex.git] / litex / build /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
drwxr-xr-x - altera
-rw-r--r-- 12288 generic_platform.py
-rw-r--r-- 992 generic_programmer.py
drwxr-xr-x - lattice
-rw-r--r-- 924 openocd.py
drwxr-xr-x - sim
-rw-r--r-- 1507 tools.py
drwxr-xr-x - xilinx