targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
[litex.git] / litex / gen /
drwxr-xr-x   ..
-rw-r--r-- 59 __init__.py
-rw-r--r-- 195 common.py
drwxr-xr-x - fhdl
drwxr-xr-x - sim