soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex / gen /
drwxr-xr-x   ..
-rw-r--r-- 59 __init__.py
-rw-r--r-- 195 common.py
drwxr-xr-x - fhdl
drwxr-xr-x - sim