build: add sha-1/date to generated verilog, change git_version to git_revision
[litex.git] / litex / gen /
drwxr-xr-x   ..
-rw-r--r-- 59 __init__.py
-rw-r--r-- 195 common.py
drwxr-xr-x - fhdl
drwxr-xr-x - sim