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soc/integration/csr_bridge: use registered version only when SDRAM is present.
[litex.git] / litex / soc / cores / cpu / serv /
drwxr-xr-x   ..
-rw-r--r-- 47 __init__.py blob | history | raw
-rw-r--r-- 75 boot-helper.S blob | history | raw
-rw-r--r-- 2748 core.py blob | history | raw
-rw-r--r-- 1093 crt0.S blob | history | raw
-rw-r--r-- 54 irq.h blob | history | raw
-rw-r--r-- 372 system.h blob | history | raw