soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex / soc / integration /
drwxr-xr-x   ..
-rw-r--r-- 104 __init__.py
-rwxr-xr-x 7783 builder.py
-rw-r--r-- 6655 cpu_interface.py
-rw-r--r-- 16973 soc_core.py
-rw-r--r-- 4471 soc_sdram.py