soc/intergration/soc_core: don't delete uart/timer0 interrupts
[litex.git] / litex / soc / integration /
drwxr-xr-x   ..
-rw-r--r-- 104 __init__.py
-rw-r--r-- 7599 builder.py
-rw-r--r-- 5877 cpu_interface.py
-rw-r--r-- 9355 sdram_init.py
-rw-r--r-- 13588 soc_core.py
-rw-r--r-- 4314 soc_sdram.py