build/sim: allow defining start/end cycles for tracing
[litex.git] / litex / tools /
drwxr-xr-x   ..
-rw-r--r-- 1 __init__.py
-rw-r--r-- 2333 litex_client.py
-rwxr-xr-x 1917 litex_read_verilog.py
-rwxr-xr-x 6816 litex_server.py
-rwxr-xr-x 9273 litex_sim.py
-rwxr-xr-x 11109 litex_term.py
drwxr-xr-x - remote