soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex / utils /
drwxr-xr-x   ..
-rwxr-xr-x 1917 litex_read_verilog.py
-rwxr-xr-x 4651 litex_server.py
-rwxr-xr-x 8691 litex_sim.py
-rwxr-xr-x 10519 litex_term.py