targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
[litex.git] / litex /
drwxr-xr-x   ..
-rw-r--r-- 48 __init__.py
drwxr-xr-x - boards
drwxr-xr-x - build
drwxr-xr-x - gen
drwxr-xr-x - soc