soc/integration/cpu_interface: generate name for Memories in get_csr_header
[litex.git] / litex /
drwxr-xr-x   ..
-rw-r--r-- 48 __init__.py
drwxr-xr-x - boards
drwxr-xr-x - build
drwxr-xr-x - gen
drwxr-xr-x - soc
drwxr-xr-x - utils