build/microsemi/libero_soc: able to generate design script (tcl) and design constrain...
[litex.git] / litex /
drwxr-xr-x   ..
-rw-r--r-- 48 __init__.py
drwxr-xr-x - boards
drwxr-xr-x - build
drwxr-xr-x - gen
drwxr-xr-x - soc