soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
[litex.git] / litex /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
drwxr-xr-x - boards
drwxr-xr-x - build
drwxr-xr-x - gen
drwxr-xr-x - soc