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vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
[nmigen.git]
/
nmigen
/
test
/
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__init__.py
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test_build_dsl.py
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test_build_plat.py
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test_build_res.py
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test_compat.py
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test_examples.py
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test_hdl_ast.py
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test_hdl_cd.py
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test_hdl_dsl.py
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test_hdl_ir.py
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test_hdl_mem.py
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test_hdl_rec.py
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test_hdl_xfrm.py
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test_lib_cdc.py
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test_lib_coding.py
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test_lib_fifo.py
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test_lib_io.py
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test_sim.py
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utils.py
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