vendor.lattice_ice40: never place an inverter on global buffer output.
[nmigen.git] / nmigen / vendor /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 12318 lattice_ice40.py
-rw-r--r-- 13354 xilinx_7series.py
-rw-r--r-- 12589 xilinx_spartan6.py