ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
[gem5.git] / src / arch / mips / isa /
drwxr-xr-x   ..
-rw-r--r-- 3733 base.isa
-rw-r--r-- 3869 bitfields.isa
-rw-r--r-- 124468 decoder.isa
drwxr-xr-x - formats
-rw-r--r-- 2984 includes.isa
-rw-r--r-- 2407 main.isa
-rw-r--r-- 7062 operands.isa