Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across...
[gem5.git] / src / arch /
drwxr-xr-x   ..
-rw-r--r-- 4961 SConscript
drwxr-xr-x - alpha
-rwxr-xr-x 66442 isa_parser.py
-rw-r--r-- 2614 isa_specific.hh
drwxr-xr-x - mips
drwxr-xr-x - sparc
drwxr-xr-x - x86