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Made regs 32-bit word aligned to match the rest of the system
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
drwxr-xr-x
..
-rw-r--r--
7344
UART.scala
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-rw-r--r--
277
UARTCtrlRegs.scala
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-rw-r--r--
1436
UARTPeriphery.scala
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