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whoops. mode-bits need to be put in MSB0 order. sigh
[openpower-isa.git]
/
src
/
openpower
/
sv
/
trans
/
drwxr-xr-x
..
-rw-r--r--
3068
pysvp64dis.py
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-rw-r--r--
59906
svp64.py
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-rw-r--r--
6626
test_pysvp64dis.py
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