add sv.bc/vs - VLset - test. truncates VL at the vector-condition-fail point
[openpower-isa.git] / src / test /
drwxr-xr-x   ..
drwxr-xr-x - basic_pypowersim
drwxr-xr-x - basic_pypowersim_fp
drwxr-xr-x - basic_svp64_trans