projects / yosys.git / tree
| drwxr-xr-x | .. | ||
| -rw-r--r-- | 653 | Makefile.inc | blob | history | raw |
| -rw-r--r-- | 2376 | anlogic_determine_init.cc | blob | history | raw |
| -rw-r--r-- | 3129 | anlogic_eqn.cc | blob | history | raw |
| -rw-r--r-- | 2361 | arith_map.v | blob | history | raw |
| -rw-r--r-- | 4052 | cells_map.v | blob | history | raw |
| -rw-r--r-- | 1604 | cells_sim.v | blob | history | raw |
| -rw-r--r-- | 939 | dram_init_16x4.vh | blob | history | raw |
| -rw-r--r-- | 201 | drams.txt | blob | history | raw |
| -rw-r--r-- | 402 | drams_map.v | blob | history | raw |
| -rw-r--r-- | 33586 | eagle_bb.v | blob | history | raw |
| -rw-r--r-- | 5792 | synth_anlogic.cc | blob | history | raw |