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Add up5k timings
[yosys.git]
/
techlibs
/
ice40
/
drwxr-xr-x
..
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.gitignore
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Makefile.inc
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abc.v
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arith_map.v
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brams.txt
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brams_init.py
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cells_map.v
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cells_sim.v
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hx8k.box
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hx8k.lut
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ice40_braminit.cc
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ice40_ffinit.cc
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ice40_ffssr.cc
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ice40_opt.cc
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ice40_unlut.cc
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latches_map.v
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synth_ice40.cc
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drwxr-xr-x
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tests
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up5k.box
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up5k.lut
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