Merge https://github.com/YosysHQ/yosys into bram_xilinx
[yosys.git] / techlibs / intel / arria10gx /
drwxr-xr-x   ..
-rw-r--r-- 2584 cells_arith.v
-rw-r--r-- 2150 cells_map.v
-rw-r--r-- 1956 cells_sim.v