abc9: generate $abc9_holes design instead of <name>$holes
[yosys.git] / techlibs / intel / cyclonev /
drwxr-xr-x   ..
-rw-r--r-- 2584 cells_arith.v
-rw-r--r-- 6542 cells_map.v
-rw-r--r-- 4880 cells_sim.v