Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
[yosys.git] / techlibs / intel / max10 /
drwxr-xr-x   ..
-rw-r--r-- 2584 cells_arith.v
-rw-r--r-- 4086 cells_map.v
-rw-r--r-- 9536 cells_sim.v