Merge pull request #2405 from byuccl/fix_xilinx_cells
[yosys.git] / techlibs / intel /
drwxr-xr-x   ..
-rw-r--r-- 901 Makefile.inc
drwxr-xr-x - common
drwxr-xr-x - cyclone10lp
drwxr-xr-x - cycloneiv
drwxr-xr-x - cycloneive
drwxr-xr-x - max10
-rw-r--r-- 8170 synth_intel.cc