Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
[yosys.git] / techlibs / intel /
drwxr-xr-x   ..
-rwxr-xr-x 1589 Makefile.inc
drwxr-xr-x - a10gx
drwxr-xr-x - common
drwxr-xr-x - cycloneiv
drwxr-xr-x - cycloneive
drwxr-xr-x - cyclonev
drwxr-xr-x - max10
-rwxr-xr-x 8234 synth_intel.cc