abc9: generate $abc9_holes design instead of <name>$holes
[yosys.git] / techlibs / intel_alm /
drwxr-xr-x   ..
-rw-r--r-- 1215 Makefile.inc
drwxr-xr-x - common
-rw-r--r-- 8065 synth_intel_alm.cc